Hi
Assorted testcase updates to reflect codegen differences on
Power9 versus Power8 and earlier systems.
Tested on P9, this is expected to clean up the majority of the
currently failing tests on that system.
OK for trunk?
Thanks
-Will
2017-11-17 Will Schmidt <will_schm...@vnet.ibm.com>
[testsuite]
* fold-vec-neg-int.c: Specify -mcpu=power8
* fold-vec-neg-int.p9.c: New.
* fold-vec-neg-longlong.c: Specify -mcpu=power8
* fold-vec-neg-longlong.p9.c: New.
* fold-vec-splat-8.c: Add p9 instruction to expect list.
* fold-vec-splats-int.c: Add p9 instruction to expect list.
* fold-vec-splats-longlong.c: Add p9 instruction to expect list.
* fold-vec-abs-char-fwrapv.c: Add xxspltib insn to expected output.
* fold-vec-abs-char.c: Add xxspltib insn to expected output list.
* fold-vec-abs-int-fwrapv.c: Specify -mcpu=power8.
* fold-vec-abs-int.c: Specify -mcpu=power8.
* fold-vec-abs-longlong-fwrapv.c: Specify -mcpu=power8.
* fold-vec-abs-longlong.c: Specify -mcpu=power8
* fold-vec-abs-short-fwrapv.c: Specify -mcpu=power8
* fold-vec-abs-short.c: Specify -mcpu=power8
* fold-vec-cmp-char.c: Specify -mcpu=power8
* fold-vec-cmp-int.c: Specify -mcpu=power8
* fold-vec-cmp-longlong.c: Specify -mcpu=power8
* fold-vec-cmp-short.c: Specify -mcpu=power8
* fold-vec-ld-char.c: Add lxv insn to expected output.
* fold-vec-ld-double.c: Add lxv insn to expected output.
* fold-vec-ld-float.c: Add lxv insn to expected output.
* fold-vec-ld-int.c: Add lxv insn to expected output.
* fold-vec-ld-longlong.c: Add lxv insn to expected output.
* fold-vec-ld-short.c: Add lxv insn to expected output.
* fold-vec-mult-int128-p9.c: Add maddld insn to expected output.
* fold-vec-neg-int.c: Specify -mcpu=power8
* fold-vec-neg-int.p9.c: New.
* fold-vec-neg-longlong.c: Specify -mcpu=power8
* fold-vec-neg-longlong.p9.c: New.
* fold-vec-splat-8.c : Add vspltisb to expected output.
* fold-vec-splats-int.c : Add mtvsrws to expected output.
* fold-vec-splats-longlong.c : Add mtvsrdd to expected output.
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char-fwrapv.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char-fwrapv.c
index 739f06e..29efd5e 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char-fwrapv.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char-fwrapv.c
@@ -11,8 +11,9 @@ vector signed char
test2 (vector signed char x)
{
return vec_abs (x);
}
-/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+//# Power9 added xxspltib instruction.
+/* { dg-final { scan-assembler-times "vspltisw|vxor|xxspltib" 1 } } */
/* { dg-final { scan-assembler-times "vsububm" 1 } } */
/* { dg-final { scan-assembler-times "vmaxsb" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char.c
index 239c919..3639617 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char.c
@@ -11,8 +11,9 @@ vector signed char
test2 (vector signed char x)
{
return vec_abs (x);
}
-/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */
+//# Power9 added xxspltib instruction.
+/* { dg-final { scan-assembler-times "vspltisw|vxor|xxspltib" 1 } } */
/* { dg-final { scan-assembler-times "vsububm" 1 } } */
/* { dg-final { scan-assembler-times "vmaxsb" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c
index 34dead4..9dfc90b 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c
@@ -1,11 +1,11 @@
/* Verify that overloaded built-ins for vec_abs with int
inputs produce the right results. */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -O2 -fwrapv" } */
+/* { dg-options "-maltivec -O2 -fwrapv -mcpu=power8" } */
#include <altivec.h>
vector signed int
test1 (vector signed int x)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c
index 77d9ca5..81b82d9 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c
@@ -1,11 +1,11 @@
/* Verify that overloaded built-ins for vec_abs with int
inputs produce the right results. */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -O2" } */
+/* { dg-options "-maltivec -O2 -mcpu=power8" } */
#include <altivec.h>
vector signed int
test1 (vector signed int x)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c
index 934618b..3b4107d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c
@@ -1,11 +1,11 @@
/* Verify that overloaded built-ins for vec_abs with long long
inputs produce the right results. */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mpower8-vector -O2 -fwrapv" } */
+/* { dg-options "-mpower8-vector -O2 -fwrapv -mcpu=power8" } */
#include <altivec.h>
vector signed long long
test3 (vector signed long long x)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c
index 5b59d19..fff0ea2 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c
@@ -1,11 +1,11 @@
/* Verify that overloaded built-ins for vec_abs with long long
inputs produce the right results. */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mpower8-vector -O2" } */
+/* { dg-options "-mpower8-vector -O2 -mcpu=power8" } */
#include <altivec.h>
vector signed long long
test3 (vector signed long long x)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short-fwrapv.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short-fwrapv.c
index 2562179..eeaec77 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short-fwrapv.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short-fwrapv.c
@@ -1,11 +1,11 @@
/* Verify that overloaded built-ins for vec_abs with short
inputs produce the right results. */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -O2 -fwrapv" } */
+/* { dg-options "-maltivec -O2 -fwrapv -mcpu=power8" } */
#include <altivec.h>
vector signed short
test3 (vector signed short x)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short.c
index d312000..73cf1aa 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short.c
@@ -1,11 +1,11 @@
/* Verify that overloaded built-ins for vec_abs with short
inputs produce the right results. */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -O2" } */
+/* { dg-options "-maltivec -O2 -mcpu=power8" } */
#include <altivec.h>
vector signed short
test3 (vector signed short x)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.c
index 3a1aa60..1c61df9 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.c
@@ -1,11 +1,11 @@
/* Verify that overloaded built-ins for vec_cmp{eq,ge,gt,le,lt,ne} with
char inputs produce the right code. */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mpower8-vector -O2" } */
+/* { dg-options "-mpower8-vector -O2 -mcpu=power8" } */
#include <altivec.h>
vector bool char
test3_eq (vector signed char x, vector signed char y)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.c
index d53994d..c7b7aea 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.c
@@ -1,11 +1,11 @@
/* Verify that overloaded built-ins for vec_cmp with int
inputs produce the right code. */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mpower8-vector -O2" } */
+/* { dg-options "-mpower8-vector -O2 -mcpu=power8" } */
#include <altivec.h>
vector bool int
test3_eq (vector signed int x, vector signed int y)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-longlong.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-longlong.c
index 536ee75..de34b6b 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-longlong.c
@@ -1,11 +1,11 @@
/* Verify that overloaded built-ins for vec_cmp with long long
inputs produce the right code. */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mpower8-vector -O2" } */
+/* { dg-options "-mpower8-vector -O2 -mcpu=power8" } */
#include <altivec.h>
vector bool long long
test3_eq (vector signed long long x, vector signed long long y)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.c
index 6067669..5613382 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.c
@@ -1,11 +1,11 @@
/* Verify that overloaded built-ins for vec_cmp with short
inputs produce the right code. */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mpower8-vector -O2" } */
+/* { dg-options "-maltivec -O2 -mcpu=power8" } */
#include <altivec.h>
vector bool short
test3_eq (vector signed short x, vector signed short y)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-char.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-char.c
index f9ef3e0..07385dd 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-char.c
@@ -65,7 +65,8 @@ vector bool char
testld_cst_vbc (vector bool char vbc2)
{
return vec_ld (80, &vbc2);
}
-/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxvw4x\M} 10 } } */
+/* # power9 added lxv. */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxvw4x\M|\mlxv\M}
10 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-double.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-double.c
index 9c6fbb2..e6266ec 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-double.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-double.c
@@ -17,6 +17,7 @@ vector double
testld_cst_vd (long long ll1, vector double vd)
{
return vec_ld (16, &vd);
}
-/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M} 2 } } */
+/* # power9 added lxv. */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-float.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-float.c
index eca847a..2fc4457 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-float.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-float.c
@@ -29,9 +29,10 @@ vector float
testld_cst_f (float f2)
{
return vec_ld (16, &f2);
}
+/* # power9 added lxv. */
// lvx - generated by ll_vf and ll_f
// lxvd2x - generated by cst_vf and cst_f
-/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M} 4 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-int.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-int.c
index 5dc6df6..872c02e 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-int.c
@@ -65,7 +65,8 @@ vector bool int
testld_cst_vbi (vector bool int vbi2)
{
return vec_ld (80, &vbi2);
}
-/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxvw4x\M} 10 } } */
+/* # power9 added lxv. */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxvw4x\M|\mlxv\M}
10 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-longlong.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-longlong.c
index db4a879..f9e5c6d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-longlong.c
@@ -41,7 +41,8 @@ vector bool long long
testld_cst_vbl (vector bool long vbl2)
{
return vec_ld (48, &vbl2);
}
-/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M} 6 } } */
+/* # power9 added lxv. */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-short.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-short.c
index 5e42844..1e93204 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-short.c
@@ -65,7 +65,8 @@ vector bool short
testld_cst_vbs (vector bool short vbs2)
{
return vec_ld (80, &vbs2);
}
-/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxvw4x\M} 10 } } */
+/* # power9 added lxv. */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxvw4x\M|\mlxv\M}
10 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c
index 6571884..1c1acec 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c
@@ -1,7 +1,7 @@
/* Verify that overloaded built-ins for vec_mul with __int128
- inputs produce the right results. */
+ inputs produce the right code. */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-require-effective-target int128 } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
"-mcpu=power9" } } */
@@ -20,7 +20,8 @@ vector unsigned __int128
test2 (vector unsigned __int128 x, vector unsigned __int128 y)
{
return vec_mul (x, y);
}
-/* { dg-final { scan-assembler-times {\mmulld\M} 4 } } */
+/* p9 adds maddld instruction */
+/* { dg-final { scan-assembler-times {\mmulld\M|\mmaddld\M} 6 } } */
/* { dg-final { scan-assembler-times {\mmulhdu\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.c
index d6ca128..d2db982 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.c
@@ -1,11 +1,11 @@
/* Verify that overloaded built-ins for vec_neg with int
inputs produce the right code. */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -O2" } */
+/* { dg-options "-maltivec -O2 -mcpu=power8" } */
#include <altivec.h>
vector signed int
test1 (vector signed int x)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p9.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p9.c
new file mode 100644
index 0000000..3b895cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p9.c
@@ -0,0 +1,16 @@
+/* Verify that overloaded built-ins for vec_neg with int
+ inputs produce the right code. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mcpu=power9" } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector signed int x)
+{
+ return vec_neg (x);
+}
+
+/* { dg-final { scan-assembler-times "vnegw" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.c
index 48f7178..e1b87df 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.c
@@ -1,11 +1,11 @@
/* Verify that overloaded built-ins for vec_neg with long long
inputs produce the right code. */
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mpower8-vector -O2" } */
+/* { dg-options "-mpower8-vector -O2 -mcpu=power8" } */
#include <altivec.h>
vector signed long long
test3 (vector signed long long x)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p9.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p9.c
new file mode 100644
index 0000000..b92f5ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p9.c
@@ -0,0 +1,16 @@
+/* Verify that overloaded built-ins for vec_neg with long long
+ inputs produce the right code. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2 -mcpu=power9" } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x)
+{
+ return vec_neg (x);
+}
+
+/* { dg-final { scan-assembler-times "vnegd" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-8.c
index 679fcb3..127b3c8 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-8.c
@@ -41,6 +41,7 @@ vector unsigned char
testuc_3 ()
{
return vec_splat_u8 (15);
}
-/* { dg-final { scan-assembler-times "vspltisb" 6 } } */
+// power9 added xxspltib VSX Vector Splat Immediate Byte.
+/* { dg-final { scan-assembler-times "xxspltib|vspltisb" 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splats-int.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-splats-int.c
index 6671523..8cb689b 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splats-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splats-int.c
@@ -17,6 +17,7 @@ vector unsigned int
test3u (unsigned int x)
{
return vec_splats (x);
}
-/* { dg-final { scan-assembler-times {\mvspltw\M|\mxxspltw\M} 2 } } */
+// Power9 adds 'mtvsrws', Move to VSR Word & Splat
+/* { dg-final { scan-assembler-times {\mvspltw\M|\mxxspltw\M|\mmtvsrws\M} 2 }
} */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splats-longlong.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-splats-longlong.c
index c5884ba..b8467d3 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splats-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splats-longlong.c
@@ -17,6 +17,7 @@ vector unsigned long long
test3u (unsigned long long x)
{
return vec_splats (x);
}
-/* { dg-final { scan-assembler-times "xxpermdi" 2 } } */
+// power9 adds Move To VSR Double Dword
+/* { dg-final { scan-assembler-times "xxpermdi|mtvsrdd" 2 } } */
