On Tue, Nov 07, 2017 at 09:28:54AM +0100, Uros Bizjak wrote:
> Yes, I am aware that ix86_binary_operator_ok (and corresponding
> expander fixup) is way too complex for SSE patterns, but until AVX,
> this function handled all patterns in an universal way. Please also
> note, that the intention of the corresponding expander fixup function
> is to make expanded pattern like final instruction as much as possible
> (e.g. emit memory operand of a commutative operator as operand2, or
> push memory operands to a register). I believe that recent
> improvements in RA made these functions somehow obsolete, but I still
> think it is beneficial to fixup memory operands at expansion time,
> even for AVX.
Actually, part of what I've said is just wrong, sorry for that.
There is really no difference between SSE and AVX, if we have:
(define_insn "*<plusminus_insn><mode>3<mask_name><round_name>"
[(set (match_operand:VF 0 "register_operand" "=x,v")
(plusminus:VF
(match_operand:VF 1 "<round_nimm_predicate>" "<comm>0,v")
(match_operand:VF 2 "<round_nimm_predicate>"
"xBm,<round_constraint>")))]
"TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) &&
<mask_mode512bit_condition> && <round_mode512bit_condition>"
then we need to ensure if <comm> expands to nothing that operands[1]
is not a MEM, for both SSE and AVX (well, if substing the predicate
is register_operand and we don't allow any MEM already).
What remains true is that for patterns which are always commutative,
with explicit %, ix86_binary_operator_ok works, but is unnecessarily
heavy and !(MEM_P (operands[1]) && MEM_P (operands[2])) can do the job
just fine.
For non-commutative patterns where the predicates don't ensure operands[1]
is not memory, we really need to ensure that operands[1] is not a MEM,
the constraints say so, but the predicates don't.
The reason I've misidentified the original problem was that the pattern
I was looking at was EQ, and ix86_swap_binary_operands_p only treated
RTX_COMM_ARITH as commutative, but EQ/NE are RTX_COMM_COMPARE.
That also means that we need those ix86_fixup_binary_operands_no_copy
in the expanders and that they do the right job.
So, either we can just apply the i386.c hunk(s) of the following
(so far untested) patch, or if you want, the sse.md part is a cleanup
which doesn't really change behavior of anything.
2017-11-07 Jakub Jelinek <ja...@redhat.com>
PR target/82855
* config/i386/i386.c (ix86_swap_binary_operands_p): Treat
RTX_COMM_COMPARE as commutative as well.
(ix86_binary_operator_ok): Formatting fix.
* config/i386/sse.md (*mul<mode>3<mask_name><round_name>,
*<code><mode>3<mask_name><round_saeonly_name>,
*<code><mode>3<mask_name>, *<code>tf3, *mul<mode>3<mask_name>,
*<s>mul<mode>3_highpart<mask_name>,
*vec_widen_umult_even_v16si<mask_name>,
*vec_widen_umult_even_v8si<mask_name>,
*vec_widen_umult_even_v4si<mask_name>,
*vec_widen_smult_even_v16si<mask_name>,
*vec_widen_smult_even_v8si<mask_name>, *sse4_1_mulv2siv2di3<mask_name>,
*avx2_pmaddwd, *sse2_pmaddwd, *<sse4_1_avx2>_mul<mode>3<mask_name>,
*avx2_<code><mode>3, *avx512f_<code><mode>3<mask_name>,
*sse4_1_<code><mode>3<mask_name>, *<code>v8hi3,
*sse4_1_<code><mode>3<mask_name>, *<code>v16qi3, *avx2_eq<mode>3,
<avx512>_eq<mode>3<mask_scalar_merge_name>_1, *sse4_1_eqv2di3,
*sse2_eq<mode>3, <mask_codefor><code><mode>3<mask_name>,
*<code><mode>3, *<sse2_avx2>_uavg<mode>3<mask_name>,
*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>, *ssse3_pmulhrswv4hi3): Use
!(MEM_P (operands[1]) && MEM_P (operands[2])) condition instead of
ix86_binary_operator_ok. Formatting fixes.
(*<plusminus_insn><mode>3<mask_name><round_name>,
*<plusminus_insn><mode>3, *<plusminus_insn><mode>3_m): Formatting
fixes.
--- gcc/config/i386/i386.c.jj 2017-11-07 08:45:21.000000000 +0100
+++ gcc/config/i386/i386.c 2017-11-07 10:25:14.118981090 +0100
@@ -19778,7 +19778,8 @@ ix86_swap_binary_operands_p (enum rtx_co
rtx src2 = operands[2];
/* If the operation is not commutative, we can't do anything. */
- if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
+ if (GET_RTX_CLASS (code) != RTX_COMM_ARITH
+ && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
return false;
/* Highest priority is that src1 should match dst. */
@@ -20009,7 +20010,7 @@ ix86_binary_operator_ok (enum rtx_code c
/* If the destination is memory, we must have a matching source operand. */
if (MEM_P (dst) && !rtx_equal_p (dst, src1))
- return false;
+ return false;
/* Source 1 cannot be a constant. */
if (CONSTANT_P (src1))
--- gcc/config/i386/sse.md.jj 2017-11-06 17:23:10.000000000 +0100
+++ gcc/config/i386/sse.md 2017-11-07 10:36:38.292598742 +0100
@@ -1602,7 +1602,8 @@ (define_insn "*<plusminus_insn><mode>3<m
(plusminus:VF
(match_operand:VF 1 "<round_nimm_predicate>" "<comm>0,v")
(match_operand:VF 2 "<round_nimm_predicate>"
"xBm,<round_constraint>")))]
- "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) &&
<mask_mode512bit_condition> && <round_mode512bit_condition>"
+ "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
+ && <mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
v<plusminus_mnemonic><ssemodesuffix>\t{<round_mask_op3>%2, %1,
%0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}"
@@ -1641,7 +1642,9 @@ (define_insn "*mul<mode>3<mask_name><rou
(mult:VF
(match_operand:VF 1 "<round_nimm_predicate>" "%0,v")
(match_operand:VF 2 "<round_nimm_predicate>"
"xBm,<round_constraint>")))]
- "TARGET_SSE && ix86_binary_operator_ok (MULT, <MODE>mode, operands) &&
<mask_mode512bit_condition> && <round_mode512bit_condition>"
+ "TARGET_SSE
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))
+ && <mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
mul<ssemodesuffix>\t{%2, %0|%0, %2}
vmul<ssemodesuffix>\t{<round_mask_op3>%2, %1,
%0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}"
@@ -1953,7 +1956,8 @@ (define_insn "*<code><mode>3<mask_name><
(smaxmin:VF
(match_operand:VF 1 "<round_saeonly_nimm_predicate>" "%0,v")
(match_operand:VF 2 "<round_saeonly_nimm_predicate>"
"xBm,<round_saeonly_constraint>")))]
- "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
+ "TARGET_SSE
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))
&& <mask_mode512bit_condition> && <round_saeonly_mode512bit_condition>"
"@
<maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
@@ -3197,7 +3201,7 @@ (define_insn "*<code><mode>3<mask_name>"
(match_operand:VF_128_256 1 "vector_operand" "%0,x,v,v")
(match_operand:VF_128_256 2 "vector_operand" "xBm,xm,vm,vm")))]
"TARGET_SSE && <mask_avx512vl_condition>
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
static char buf[128];
const char *ops;
@@ -3261,7 +3265,7 @@ (define_insn "*<code><mode>3<mask_name>"
(any_logic:VF_512
(match_operand:VF_512 1 "nonimmediate_operand" "%v")
(match_operand:VF_512 2 "nonimmediate_operand" "vm")))]
- "TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
static char buf[128];
const char *ops;
@@ -3515,8 +3519,7 @@ (define_insn "*<code>tf3"
(any_logic:TF
(match_operand:TF 1 "vector_operand" "%0,x,v,v")
(match_operand:TF 2 "vector_operand" "xBm,xm,vm,v")))]
- "TARGET_SSE
- && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
+ "TARGET_SSE && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
static char buf[128];
const char *ops;
@@ -9988,8 +9991,7 @@ (define_insn "*<plusminus_insn><mode>3"
(plusminus:VI_AVX2
(match_operand:VI_AVX2 1 "vector_operand" "<comm>0,v")
(match_operand:VI_AVX2 2 "vector_operand" "xBm,vm")))]
- "TARGET_SSE2
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"@
p<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1,
%0<mask_operand3>|%0<mask_operand3>, %1, %2}"
@@ -10007,8 +10009,7 @@ (define_insn "*<plusminus_insn><mode>3_m
(match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm"))
(match_operand:VI48_AVX512VL 3 "vector_move_operand" "0C")
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX512F
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3,
%1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix" "evex")
@@ -10073,8 +10074,7 @@ (define_insn "*mul<mode>3<mask_name>"
[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,v")
(mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "vector_operand" "%0,v")
(match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm")))]
- "TARGET_SSE2
- && ix86_binary_operator_ok (MULT, <MODE>mode, operands)
+ "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))
&& <mask_mode512bit_condition> && <mask_avx512bw_condition>"
"@
pmullw\t{%2, %0|%0, %2}
@@ -10109,8 +10109,7 @@ (define_insn "*<s>mul<mode>3_highpart<ma
(any_extend:<ssedoublemode>
(match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm")))
(const_int 16))))]
- "TARGET_SSE2
- && ix86_binary_operator_ok (MULT, <MODE>mode, operands)
+ "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))
&& <mask_mode512bit_condition> && <mask_avx512bw_condition>"
"@
pmulh<u>w\t{%2, %0|%0, %2}
@@ -10158,7 +10157,7 @@ (define_insn "*vec_widen_umult_even_v16s
(const_int 4) (const_int 6)
(const_int 8) (const_int 10)
(const_int 12) (const_int 14)])))))]
- "TARGET_AVX512F && ix86_binary_operator_ok (MULT, V16SImode, operands)"
+ "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseimul")
(set_attr "prefix_extra" "1")
@@ -10195,7 +10194,7 @@ (define_insn "*vec_widen_umult_even_v8si
(parallel [(const_int 0) (const_int 2)
(const_int 4) (const_int 6)])))))]
"TARGET_AVX2 && <mask_avx512vl_condition>
- && ix86_binary_operator_ok (MULT, V8SImode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseimul")
(set_attr "prefix" "maybe_evex")
@@ -10227,7 +10226,7 @@ (define_insn "*vec_widen_umult_even_v4si
(match_operand:V4SI 2 "vector_operand" "xBm,vm")
(parallel [(const_int 0) (const_int 2)])))))]
"TARGET_SSE2 && <mask_avx512vl_condition>
- && ix86_binary_operator_ok (MULT, V4SImode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
pmuludq\t{%2, %0|%0, %2}
vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
@@ -10274,7 +10273,7 @@ (define_insn "*vec_widen_smult_even_v16s
(const_int 4) (const_int 6)
(const_int 8) (const_int 10)
(const_int 12) (const_int 14)])))))]
- "TARGET_AVX512F && ix86_binary_operator_ok (MULT, V16SImode, operands)"
+ "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseimul")
(set_attr "prefix_extra" "1")
@@ -10310,8 +10309,7 @@ (define_insn "*vec_widen_smult_even_v8si
(match_operand:V8SI 2 "nonimmediate_operand" "vm")
(parallel [(const_int 0) (const_int 2)
(const_int 4) (const_int 6)])))))]
- "TARGET_AVX2
- && ix86_binary_operator_ok (MULT, V8SImode, operands)"
+ "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseimul")
(set_attr "prefix_extra" "1")
@@ -10344,7 +10342,7 @@ (define_insn "*sse4_1_mulv2siv2di3<mask_
(match_operand:V4SI 2 "vector_operand" "YrBm,*xBm,vm")
(parallel [(const_int 0) (const_int 2)])))))]
"TARGET_SSE4_1 && <mask_avx512vl_condition>
- && ix86_binary_operator_ok (MULT, V4SImode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
pmuldq\t{%2, %0|%0, %2}
pmuldq\t{%2, %0|%0, %2}
@@ -10433,7 +10431,7 @@ (define_insn "*avx2_pmaddwd"
(const_int 5) (const_int 7)
(const_int 9) (const_int 11)
(const_int 13) (const_int 15)]))))))]
- "TARGET_AVX2 && ix86_binary_operator_ok (MULT, V16HImode, operands)"
+ "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "isa" "*,avx512bw")
@@ -10489,7 +10487,7 @@ (define_insn "*sse2_pmaddwd"
(vec_select:V4HI (match_dup 2)
(parallel [(const_int 1) (const_int 3)
(const_int 5) (const_int 7)]))))))]
- "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
+ "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
pmaddwd\t{%2, %0|%0, %2}
vpmaddwd\t{%2, %1, %0|%0, %1, %2}
@@ -10539,7 +10537,8 @@ (define_insn "*<sse4_1_avx2>_mul<mode>3<
(mult:VI4_AVX512F
(match_operand:VI4_AVX512F 1 "vector_operand" "%0,0,v")
(match_operand:VI4_AVX512F 2 "vector_operand" "YrBm,*xBm,vm")))]
- "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, <MODE>mode, operands) &&
<mask_mode512bit_condition>"
+ "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))
+ && <mask_mode512bit_condition>"
"@
pmulld\t{%2, %0|%0, %2}
pmulld\t{%2, %0|%0, %2}
@@ -10857,7 +10856,7 @@ (define_insn "*avx2_<code><mode>3"
(maxmin:VI124_256
(match_operand:VI124_256 1 "nonimmediate_operand" "%v")
(match_operand:VI124_256 2 "nonimmediate_operand" "vm")))]
- "TARGET_AVX2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
@@ -10880,7 +10879,7 @@ (define_insn "*avx512f_<code><mode>3<mas
(maxmin:VI48_AVX512VL
(match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "%v")
(match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")))]
- "TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vp<maxmin_int><ssemodesuffix>\t{%2, %1,
%0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
@@ -10986,7 +10985,7 @@ (define_insn "*sse4_1_<code><mode>3<mask
(match_operand:VI14_128 2 "vector_operand" "YrBm,*xBm,vm")))]
"TARGET_SSE4_1
&& <mask_mode512bit_condition>
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
@@ -11002,7 +11001,7 @@ (define_insn "*<code>v8hi3"
(smaxmin:V8HI
(match_operand:V8HI 1 "vector_operand" "%0,x,v")
(match_operand:V8HI 2 "vector_operand" "xBm,xm,vm")))]
- "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)"
+ "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
p<maxmin_int>w\t{%2, %0|%0, %2}
vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}
@@ -11071,7 +11070,7 @@ (define_insn "*sse4_1_<code><mode>3<mask
(match_operand:VI24_128 2 "vector_operand" "YrBm,*xBm,vm")))]
"TARGET_SSE4_1
&& <mask_mode512bit_condition>
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
@@ -11087,7 +11086,7 @@ (define_insn "*<code>v16qi3"
(umaxmin:V16QI
(match_operand:V16QI 1 "vector_operand" "%0,x,v")
(match_operand:V16QI 2 "vector_operand" "xBm,xm,vm")))]
- "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)"
+ "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
p<maxmin_int>b\t{%2, %0|%0, %2}
vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}
@@ -11118,7 +11117,7 @@ (define_insn "*avx2_eq<mode>3"
(eq:VI_256
(match_operand:VI_256 1 "nonimmediate_operand" "%x")
(match_operand:VI_256 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX2 && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
+ "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecmp")
(set_attr "prefix_extra" "1")
@@ -11149,7 +11148,7 @@ (define_insn "<avx512>_eq<mode>3<mask_sc
[(match_operand:VI12_AVX512VL 1 "register_operand" "%v")
(match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")]
UNSPEC_MASKED_EQ))]
- "TARGET_AVX512F && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
+ "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpcmpeq<ssemodesuffix>\t{%2, %1,
%0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
[(set_attr "type" "ssecmp")
(set_attr "prefix_extra" "1")
@@ -11162,7 +11161,7 @@ (define_insn "<avx512>_eq<mode>3<mask_sc
[(match_operand:VI48_AVX512VL 1 "register_operand" "%v")
(match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")]
UNSPEC_MASKED_EQ))]
- "TARGET_AVX512F && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
+ "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpcmpeq<ssemodesuffix>\t{%2, %1,
%0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
[(set_attr "type" "ssecmp")
(set_attr "prefix_extra" "1")
@@ -11174,7 +11173,7 @@ (define_insn "*sse4_1_eqv2di3"
(eq:V2DI
(match_operand:V2DI 1 "vector_operand" "%0,0,x")
(match_operand:V2DI 2 "vector_operand" "YrBm,*xBm,xm")))]
- "TARGET_SSE4_1 && ix86_binary_operator_ok (EQ, V2DImode, operands)"
+ "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
pcmpeqq\t{%2, %0|%0, %2}
pcmpeqq\t{%2, %0|%0, %2}
@@ -11191,7 +11190,7 @@ (define_insn "*sse2_eq<mode>3"
(match_operand:VI124_128 1 "vector_operand" "%0,x")
(match_operand:VI124_128 2 "vector_operand" "xBm,xm")))]
"TARGET_SSE2 && !TARGET_XOP
- && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
pcmpeq<ssemodesuffix>\t{%2, %0|%0, %2}
vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
@@ -11656,7 +11655,7 @@ (define_insn "<mask_codefor><code><mode>
(match_operand:VI48_AVX_AVX512F 1 "vector_operand" "%0,x,v")
(match_operand:VI48_AVX_AVX512F 2 "vector_operand" "xBm,xm,vm")))]
"TARGET_SSE && <mask_mode512bit_condition>
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
static char buf[64];
const char *ops;
@@ -11753,10 +11752,10 @@ (define_insn "<mask_codefor><code><mode>
(define_insn "*<code><mode>3"
[(set (match_operand:VI12_AVX_AVX512F 0 "register_operand" "=x,x,v")
- (any_logic: VI12_AVX_AVX512F
+ (any_logic:VI12_AVX_AVX512F
(match_operand:VI12_AVX_AVX512F 1 "vector_operand" "%0,x,v")
(match_operand:VI12_AVX_AVX512F 2 "vector_operand" "xBm,xm,vm")))]
- "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "TARGET_SSE && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
static char buf[64];
const char *ops;
@@ -14067,7 +14066,7 @@ (define_insn "*<sse2_avx2>_uavg<mode>3<m
(match_operand:VI12_AVX2 <mask_expand_op3> "const1_operand"))
(const_int 1))))]
"TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>
- && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
pavg<ssemodesuffix>\t{%2, %0|%0, %2}
vpavg<ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
@@ -14741,7 +14740,7 @@ (define_insn "*<ssse3_avx2>_pmulhrsw<mod
(match_operand:VI2_AVX2 3 "const1_operand"))
(const_int 1))))]
"TARGET_SSSE3 && <mask_mode512bit_condition> && <mask_avx512bw_condition>
- && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
pmulhrsw\t{%2, %0|%0, %2}
vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}
@@ -14767,7 +14766,7 @@ (define_insn "*ssse3_pmulhrswv4hi3"
(const_int 14))
(match_operand:V4HI 3 "const1_operand"))
(const_int 1))))]
- "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
+ "TARGET_SSSE3 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"pmulhrsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseimul")
(set_attr "prefix_extra" "1")
Jakub
