On Mon, Nov 6, 2017 at 10:18 PM, Jakub Jelinek <[email protected]> wrote:
> Hi!
>
> As this patch shows, we have tons of ix86_binary_operator_ok calls
> in sse.md patterns, but I believe those are inappropriate in all these
> spots, the function is for normal 2 operand binary instructions, where
> we require that if one operand is memory, the destination is as well and
> they match. That is generally not the case for 3 operand SSE*/AVX*
> instructions, where the destination is always a register, and one of the
> other operands can be a memory. All we care about and is what we express
> in condition on many other sse.md instructions is that at most one input
> operand is a memory, never both.
!(MEM_P (operands[1]) && MEM_P (operands[2])) applies to AVX patterns
only. Please note that ix86_binary_operator_ok also handles dst/src1
operand matching and commutative operands in non-AVX SSE patterns.
Looking at the patch, perhaps we should introduce
ix86_fixup_sse_binary_operator and ix86_sse_binary_operator_ok that
would bypass most of ix86_{fixup_,}binary_operator{,_ok} operand
handling for TARGET_AVX? This way, we will still allow memory operands
as operand1 and operand2 for commutative operators in AVX and non-AVX
patterns and match src1 and dst of non-AVX patterns.
Uros.
> So, the following patch changes all those spots, I've left in only one
> call on movhlps with possible offsetable memory destination, will need to
> think more about that one.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
>
> 2017-11-06 Jakub Jelinek <[email protected]>
>
> PR target/82855
> * config/i386/sse.md (*<plusminus_insn><mode>3<mask_name><round_name>,
> *mul<mode>3<mask_name><round_name>,
> *<code><mode>3<mask_name><round_saeonly_name>,
> *<code><mode>3<mask_name>, *<code>tf3, *<plusminus_insn><mode>3,
> *<plusminus_insn><mode>3_mask, *<plusminus_insn><mode>3_mask,
> *<sse2_avx2>_<plusminus_insn><mode>3<mask_name>,
> *mul<mode>3<mask_name>, *<s>mul<mode>3_highpart<mask_name>,
> *vec_widen_umult_even_v16si<mask_name>,
> *vec_widen_umult_even_v8si<mask_name>,
> *vec_widen_umult_even_v4si<mask_name>,
> *vec_widen_smult_even_v16si<mask_name>,
> *vec_widen_smult_even_v8si<mask_name>,
> *sse4_1_mulv2siv2di3<mask_name>,
> *avx2_pmaddwd, *sse2_pmaddwd, *<sse4_1_avx2>_mul<mode>3<mask_name>,
> *avx2_<code><mode>3, *avx512f_<code><mode>3<mask_name>,
> *sse4_1_<code><mode>3<mask_name>, *<code>v8hi3,
> *sse4_1_<code><mode>3<mask_name>, *<code>v16qi3, *avx2_eq<mode>3,
> <avx512>_eq<mode>3<mask_scalar_merge_name>_1, *sse4_1_eqv2di3,
> *sse2_eq<mode>3, <mask_codefor><code><mode>3<mask_name>,
> *<code><mode>3, *<sse2_avx2>_uavg<mode>3<mask_name>,
> *<ssse3_avx2>_pmulhrsw<mode>3<mask_name>, *ssse3_pmulhrswv4hi3): Use
> !(MEM_P (operands[1]) && MEM_P (operands[2])) condition instead of
> ix86_binary_operator_ok.
>
> --- gcc/config/i386/sse.md.jj 2017-11-01 22:49:18.000000000 +0100
> +++ gcc/config/i386/sse.md 2017-11-06 11:47:55.103076500 +0100
> @@ -1602,7 +1602,10 @@ (define_insn "*<plusminus_insn><mode>3<m
> (plusminus:VF
> (match_operand:VF 1 "<round_nimm_predicate>" "<comm>0,v")
> (match_operand:VF 2 "<round_nimm_predicate>"
> "xBm,<round_constraint>")))]
> - "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) &&
> <mask_mode512bit_condition> && <round_mode512bit_condition>"
> + "TARGET_SSE
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))
> + && <mask_mode512bit_condition>
> + && <round_mode512bit_condition>"
> "@
> <plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
> v<plusminus_mnemonic><ssemodesuffix>\t{<round_mask_op3>%2, %1,
> %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}"
> @@ -1641,7 +1644,10 @@ (define_insn "*mul<mode>3<mask_name><rou
> (mult:VF
> (match_operand:VF 1 "<round_nimm_predicate>" "%0,v")
> (match_operand:VF 2 "<round_nimm_predicate>"
> "xBm,<round_constraint>")))]
> - "TARGET_SSE && ix86_binary_operator_ok (MULT, <MODE>mode, operands) &&
> <mask_mode512bit_condition> && <round_mode512bit_condition>"
> + "TARGET_SSE
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))
> + && <mask_mode512bit_condition>
> + && <round_mode512bit_condition>"
> "@
> mul<ssemodesuffix>\t{%2, %0|%0, %2}
> vmul<ssemodesuffix>\t{<round_mask_op3>%2, %1,
> %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}"
> @@ -1953,8 +1959,10 @@ (define_insn "*<code><mode>3<mask_name><
> (smaxmin:VF
> (match_operand:VF 1 "<round_saeonly_nimm_predicate>" "%0,v")
> (match_operand:VF 2 "<round_saeonly_nimm_predicate>"
> "xBm,<round_saeonly_constraint>")))]
> - "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
> - && <mask_mode512bit_condition> && <round_saeonly_mode512bit_condition>"
> + "TARGET_SSE
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))
> + && <mask_mode512bit_condition>
> + && <round_saeonly_mode512bit_condition>"
> "@
> <maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
> v<maxmin_float><ssemodesuffix>\t{<round_saeonly_mask_op3>%2, %1,
> %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_saeonly_mask_op3>}"
> @@ -3196,8 +3204,9 @@ (define_insn "*<code><mode>3<mask_name>"
> (any_logic:VF_128_256
> (match_operand:VF_128_256 1 "vector_operand" "%0,x,v,v")
> (match_operand:VF_128_256 2 "vector_operand" "xBm,xm,vm,vm")))]
> - "TARGET_SSE && <mask_avx512vl_condition>
> - && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> + "TARGET_SSE
> + && <mask_avx512vl_condition>
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> {
> static char buf[128];
> const char *ops;
> @@ -3261,7 +3270,8 @@ (define_insn "*<code><mode>3<mask_name>"
> (any_logic:VF_512
> (match_operand:VF_512 1 "nonimmediate_operand" "%v")
> (match_operand:VF_512 2 "nonimmediate_operand" "vm")))]
> - "TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> + "TARGET_AVX512F
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> {
> static char buf[128];
> const char *ops;
> @@ -3516,7 +3526,7 @@ (define_insn "*<code>tf3"
> (match_operand:TF 1 "vector_operand" "%0,x,v,v")
> (match_operand:TF 2 "vector_operand" "xBm,xm,vm,v")))]
> "TARGET_SSE
> - && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> {
> static char buf[128];
> const char *ops;
> @@ -9989,7 +9999,7 @@ (define_insn "*<plusminus_insn><mode>3"
> (match_operand:VI_AVX2 1 "vector_operand" "<comm>0,v")
> (match_operand:VI_AVX2 2 "vector_operand" "xBm,vm")))]
> "TARGET_SSE2
> - && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "@
> p<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
> vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1,
> %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
> @@ -10008,7 +10018,7 @@ (define_insn "*<plusminus_insn><mode>3_m
> (match_operand:VI48_AVX512VL 3 "vector_move_operand" "0C")
> (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
> "TARGET_AVX512F
> - && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3,
> %1, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "prefix" "evex")
> @@ -10022,7 +10032,8 @@ (define_insn "*<plusminus_insn><mode>3_m
> (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm"))
> (match_operand:VI12_AVX512VL 3 "vector_move_operand" "0C")
> (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
> - "TARGET_AVX512BW && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> + "TARGET_AVX512BW
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3,
> %1, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "prefix" "evex")
> @@ -10042,7 +10053,7 @@ (define_insn "*<sse2_avx2>_<plusminus_in
> (match_operand:VI12_AVX2 1 "vector_operand" "<comm>0,v")
> (match_operand:VI12_AVX2 2 "vector_operand" "xBm,vm")))]
> "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>
> - && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "@
> p<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
> vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1,
> %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
> @@ -10074,7 +10085,7 @@ (define_insn "*mul<mode>3<mask_name>"
> (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "vector_operand" "%0,v")
> (match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm")))]
> "TARGET_SSE2
> - && ix86_binary_operator_ok (MULT, <MODE>mode, operands)
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))
> && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
> "@
> pmullw\t{%2, %0|%0, %2}
> @@ -10110,7 +10121,7 @@ (define_insn "*<s>mul<mode>3_highpart<ma
> (match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm")))
> (const_int 16))))]
> "TARGET_SSE2
> - && ix86_binary_operator_ok (MULT, <MODE>mode, operands)
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))
> && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
> "@
> pmulh<u>w\t{%2, %0|%0, %2}
> @@ -10158,7 +10169,8 @@ (define_insn "*vec_widen_umult_even_v16s
> (const_int 4) (const_int 6)
> (const_int 8) (const_int 10)
> (const_int 12) (const_int 14)])))))]
> - "TARGET_AVX512F && ix86_binary_operator_ok (MULT, V16SImode, operands)"
> + "TARGET_AVX512F
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
> [(set_attr "type" "sseimul")
> (set_attr "prefix_extra" "1")
> @@ -10195,7 +10207,7 @@ (define_insn "*vec_widen_umult_even_v8si
> (parallel [(const_int 0) (const_int 2)
> (const_int 4) (const_int 6)])))))]
> "TARGET_AVX2 && <mask_avx512vl_condition>
> - && ix86_binary_operator_ok (MULT, V8SImode, operands)"
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
> [(set_attr "type" "sseimul")
> (set_attr "prefix" "maybe_evex")
> @@ -10227,7 +10239,7 @@ (define_insn "*vec_widen_umult_even_v4si
> (match_operand:V4SI 2 "vector_operand" "xBm,vm")
> (parallel [(const_int 0) (const_int 2)])))))]
> "TARGET_SSE2 && <mask_avx512vl_condition>
> - && ix86_binary_operator_ok (MULT, V4SImode, operands)"
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "@
> pmuludq\t{%2, %0|%0, %2}
> vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
> @@ -10274,7 +10286,8 @@ (define_insn "*vec_widen_smult_even_v16s
> (const_int 4) (const_int 6)
> (const_int 8) (const_int 10)
> (const_int 12) (const_int 14)])))))]
> - "TARGET_AVX512F && ix86_binary_operator_ok (MULT, V16SImode, operands)"
> + "TARGET_AVX512F
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
> [(set_attr "type" "sseimul")
> (set_attr "prefix_extra" "1")
> @@ -10311,7 +10324,7 @@ (define_insn "*vec_widen_smult_even_v8si
> (parallel [(const_int 0) (const_int 2)
> (const_int 4) (const_int 6)])))))]
> "TARGET_AVX2
> - && ix86_binary_operator_ok (MULT, V8SImode, operands)"
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
> [(set_attr "type" "sseimul")
> (set_attr "prefix_extra" "1")
> @@ -10344,7 +10357,7 @@ (define_insn "*sse4_1_mulv2siv2di3<mask_
> (match_operand:V4SI 2 "vector_operand" "YrBm,*xBm,vm")
> (parallel [(const_int 0) (const_int 2)])))))]
> "TARGET_SSE4_1 && <mask_avx512vl_condition>
> - && ix86_binary_operator_ok (MULT, V4SImode, operands)"
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "@
> pmuldq\t{%2, %0|%0, %2}
> pmuldq\t{%2, %0|%0, %2}
> @@ -10433,7 +10446,8 @@ (define_insn "*avx2_pmaddwd"
> (const_int 5) (const_int 7)
> (const_int 9) (const_int 11)
> (const_int 13) (const_int 15)]))))))]
> - "TARGET_AVX2 && ix86_binary_operator_ok (MULT, V16HImode, operands)"
> + "TARGET_AVX2
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "isa" "*,avx512bw")
> @@ -10489,7 +10503,8 @@ (define_insn "*sse2_pmaddwd"
> (vec_select:V4HI (match_dup 2)
> (parallel [(const_int 1) (const_int 3)
> (const_int 5) (const_int 7)]))))))]
> - "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
> + "TARGET_SSE2
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "@
> pmaddwd\t{%2, %0|%0, %2}
> vpmaddwd\t{%2, %1, %0|%0, %1, %2}
> @@ -10539,7 +10554,9 @@ (define_insn "*<sse4_1_avx2>_mul<mode>3<
> (mult:VI4_AVX512F
> (match_operand:VI4_AVX512F 1 "vector_operand" "%0,0,v")
> (match_operand:VI4_AVX512F 2 "vector_operand" "YrBm,*xBm,vm")))]
> - "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, <MODE>mode, operands) &&
> <mask_mode512bit_condition>"
> + "TARGET_SSE4_1
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))
> + && <mask_mode512bit_condition>"
> "@
> pmulld\t{%2, %0|%0, %2}
> pmulld\t{%2, %0|%0, %2}
> @@ -10857,7 +10874,8 @@ (define_insn "*avx2_<code><mode>3"
> (maxmin:VI124_256
> (match_operand:VI124_256 1 "nonimmediate_operand" "%v")
> (match_operand:VI124_256 2 "nonimmediate_operand" "vm")))]
> - "TARGET_AVX2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> + "TARGET_AVX2
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "prefix_extra" "1")
> @@ -10880,7 +10898,8 @@ (define_insn "*avx512f_<code><mode>3<mas
> (maxmin:VI48_AVX512VL
> (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "%v")
> (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")))]
> - "TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> + "TARGET_AVX512F
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vp<maxmin_int><ssemodesuffix>\t{%2, %1,
> %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
> [(set_attr "type" "sseiadd")
> (set_attr "prefix_extra" "1")
> @@ -10986,7 +11005,7 @@ (define_insn "*sse4_1_<code><mode>3<mask
> (match_operand:VI14_128 2 "vector_operand" "YrBm,*xBm,vm")))]
> "TARGET_SSE4_1
> && <mask_mode512bit_condition>
> - && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "@
> p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
> p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
> @@ -11002,7 +11021,8 @@ (define_insn "*<code>v8hi3"
> (smaxmin:V8HI
> (match_operand:V8HI 1 "vector_operand" "%0,x,v")
> (match_operand:V8HI 2 "vector_operand" "xBm,xm,vm")))]
> - "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)"
> + "TARGET_SSE2
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "@
> p<maxmin_int>w\t{%2, %0|%0, %2}
> vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}
> @@ -11071,7 +11091,7 @@ (define_insn "*sse4_1_<code><mode>3<mask
> (match_operand:VI24_128 2 "vector_operand" "YrBm,*xBm,vm")))]
> "TARGET_SSE4_1
> && <mask_mode512bit_condition>
> - && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "@
> p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
> p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
> @@ -11087,7 +11107,8 @@ (define_insn "*<code>v16qi3"
> (umaxmin:V16QI
> (match_operand:V16QI 1 "vector_operand" "%0,x,v")
> (match_operand:V16QI 2 "vector_operand" "xBm,xm,vm")))]
> - "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)"
> + "TARGET_SSE2
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "@
> p<maxmin_int>b\t{%2, %0|%0, %2}
> vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}
> @@ -11118,7 +11139,8 @@ (define_insn "*avx2_eq<mode>3"
> (eq:VI_256
> (match_operand:VI_256 1 "nonimmediate_operand" "%x")
> (match_operand:VI_256 2 "nonimmediate_operand" "xm")))]
> - "TARGET_AVX2 && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
> + "TARGET_AVX2
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "type" "ssecmp")
> (set_attr "prefix_extra" "1")
> @@ -11149,7 +11171,8 @@ (define_insn "<avx512>_eq<mode>3<mask_sc
> [(match_operand:VI12_AVX512VL 1 "register_operand" "%v")
> (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")]
> UNSPEC_MASKED_EQ))]
> - "TARGET_AVX512F && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
> + "TARGET_AVX512F
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vpcmpeq<ssemodesuffix>\t{%2, %1,
> %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
> [(set_attr "type" "ssecmp")
> (set_attr "prefix_extra" "1")
> @@ -11162,7 +11185,8 @@ (define_insn "<avx512>_eq<mode>3<mask_sc
> [(match_operand:VI48_AVX512VL 1 "register_operand" "%v")
> (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")]
> UNSPEC_MASKED_EQ))]
> - "TARGET_AVX512F && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
> + "TARGET_AVX512F
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "vpcmpeq<ssemodesuffix>\t{%2, %1,
> %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
> [(set_attr "type" "ssecmp")
> (set_attr "prefix_extra" "1")
> @@ -11174,7 +11198,8 @@ (define_insn "*sse4_1_eqv2di3"
> (eq:V2DI
> (match_operand:V2DI 1 "vector_operand" "%0,0,x")
> (match_operand:V2DI 2 "vector_operand" "YrBm,*xBm,xm")))]
> - "TARGET_SSE4_1 && ix86_binary_operator_ok (EQ, V2DImode, operands)"
> + "TARGET_SSE4_1
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "@
> pcmpeqq\t{%2, %0|%0, %2}
> pcmpeqq\t{%2, %0|%0, %2}
> @@ -11191,7 +11216,7 @@ (define_insn "*sse2_eq<mode>3"
> (match_operand:VI124_128 1 "vector_operand" "%0,x")
> (match_operand:VI124_128 2 "vector_operand" "xBm,xm")))]
> "TARGET_SSE2 && !TARGET_XOP
> - && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "@
> pcmpeq<ssemodesuffix>\t{%2, %0|%0, %2}
> vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> @@ -11656,7 +11681,7 @@ (define_insn "<mask_codefor><code><mode>
> (match_operand:VI48_AVX_AVX512F 1 "vector_operand" "%0,x,v")
> (match_operand:VI48_AVX_AVX512F 2 "vector_operand" "xBm,xm,vm")))]
> "TARGET_SSE && <mask_mode512bit_condition>
> - && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> {
> static char buf[64];
> const char *ops;
> @@ -11756,7 +11781,8 @@ (define_insn "*<code><mode>3"
> (any_logic: VI12_AVX_AVX512F
> (match_operand:VI12_AVX_AVX512F 1 "vector_operand" "%0,x,v")
> (match_operand:VI12_AVX_AVX512F 2 "vector_operand" "xBm,xm,vm")))]
> - "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> + "TARGET_SSE
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> {
> static char buf[64];
> const char *ops;
> @@ -14067,7 +14093,7 @@ (define_insn "*<sse2_avx2>_uavg<mode>3<m
> (match_operand:VI12_AVX2 <mask_expand_op3> "const1_operand"))
> (const_int 1))))]
> "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>
> - && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "@
> pavg<ssemodesuffix>\t{%2, %0|%0, %2}
> vpavg<ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1,
> %2}"
> @@ -14741,7 +14767,7 @@ (define_insn "*<ssse3_avx2>_pmulhrsw<mod
> (match_operand:VI2_AVX2 3 "const1_operand"))
> (const_int 1))))]
> "TARGET_SSSE3 && <mask_mode512bit_condition> && <mask_avx512bw_condition>
> - && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "@
> pmulhrsw\t{%2, %0|%0, %2}
> vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}
> @@ -14767,7 +14793,8 @@ (define_insn "*ssse3_pmulhrswv4hi3"
> (const_int 14))
> (match_operand:V4HI 3 "const1_operand"))
> (const_int 1))))]
> - "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
> + "TARGET_SSSE3
> + && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "pmulhrsw\t{%2, %0|%0, %2}"
> [(set_attr "type" "sseimul")
> (set_attr "prefix_extra" "1")
>
> Jakub
