On 10/12/2011 03:37 PM, David Miller wrote: > From: Richard Henderson <r...@redhat.com> > Date: Wed, 12 Oct 2011 15:32:46 -0700 > >> I suppose technically the middle-end could be improved to implement >> ashl<mode> as vashl<mode> by broadcasting the scalar, but Altivec >> is the only extant SIMD ISA that would make use of this. All of >> the others can arrange for constant shifts to be encoded into the >> insn, and so implement the ashl<mode> named pattern. > > I'm pretty sure Sparc's VIS3 can do this too, see the > '<vis3_shift_insn><vbits>_vis' patterns in sparc.md
Ok, if I read the rtl correctly, you can perform a vector shift, where each shift count comes from the corresponding element of op2. But VIS has no vector shift where the shift count comes from a single scalar (immediate or register)? If so, please rename this pattern to the "v<shift_pat_name><mode>3" form and I'll work on more middle-end support for re-use of the v<shift_pat_name> optab. r~
