From: Charles Baylis <charles.bay...@linaro.org>
Add bus widths. These use the approximation that v7 and later cores have
64bit data bus width, and earlier cores have 32 bit bus width, with the
exception of v7m.
<date> Charles Baylis <charles.bay...@linaro.org>
* config/arm/arm-protos.h (struct tune_params): New field
bus_width.
* config/arm/arm.c (arm_slowmul_tune): Initialise bus_width field.
(arm_fastmul_tune): Likewise.
(arm_strongarm_tune): Likewise.
(arm_xscale_tune): Likewise.
(arm_9e_tune): Likewise.
(arm_marvell_pj4_tune): Likewise.
(arm_v6t2_tune): Likewise.
(arm_cortex_tune): Likewise.
(arm_cortex_a8_tune): Likewise.
(arm_cortex_a7_tune): Likewise.
(arm_cortex_a15_tune): Likewise.
(arm_cortex_a35_tune): Likewise.
(arm_cortex_a53_tune): Likewise.
(arm_cortex_a57_tune): Likewise.
(arm_exynosm1_tune): Likewise.
(arm_xgene1_tune): Likewise.
(arm_cortex_a5_tune): Likewise.
(arm_cortex_a9_tune): Likewise.
(arm_cortex_a12_tune): Likewise.
(arm_cortex_a73_tune): Likewise.
(arm_v7m_tune): Likewise.
(arm_cortex_m7_tune): Likewise.
(arm_v6m_tune): Likewise.
(arm_fa726te_tune): Likewise.
Change-Id: I613e876db93ffd6f8c1e72ba483be2efc0b56d66
---
gcc/config/arm/arm-protos.h | 2 ++
gcc/config/arm/arm.c | 24 ++++++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 4538078..47a85cc 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -278,6 +278,8 @@ struct tune_params
int max_insns_inline_memset;
/* Issue rate of the processor. */
unsigned int issue_rate;
+ /* Bus width (bits). */
+ unsigned int bus_width;
/* Explicit prefetch data. */
struct
{
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index bca8a34..32001e5 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -1761,6 +1761,7 @@ const struct tune_params arm_slowmul_tune =
5, /* Max cond insns. */
8, /* Memset max inline. */
1, /* Issue rate. */
+ 32, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_TRUE,
tune_params::PREF_LDRD_FALSE,
@@ -1783,6 +1784,7 @@ const struct tune_params arm_fastmul_tune =
5, /* Max cond insns. */
8, /* Memset max inline. */
1, /* Issue rate. */
+ 32, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_TRUE,
tune_params::PREF_LDRD_FALSE,
@@ -1808,6 +1810,7 @@ const struct tune_params arm_strongarm_tune =
3, /* Max cond insns. */
8, /* Memset max inline. */
1, /* Issue rate. */
+ 32, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_TRUE,
tune_params::PREF_LDRD_FALSE,
@@ -1830,6 +1833,7 @@ const struct tune_params arm_xscale_tune =
3, /* Max cond insns. */
8, /* Memset max inline. */
1, /* Issue rate. */
+ 32, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_TRUE,
tune_params::PREF_LDRD_FALSE,
@@ -1852,6 +1856,7 @@ const struct tune_params arm_9e_tune =
5, /* Max cond insns. */
8, /* Memset max inline. */
1, /* Issue rate. */
+ 32, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_TRUE,
tune_params::PREF_LDRD_FALSE,
@@ -1874,6 +1879,7 @@ const struct tune_params arm_marvell_pj4_tune =
5, /* Max cond insns. */
8, /* Memset max inline. */
2, /* Issue rate. */
+ 32, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_TRUE,
tune_params::PREF_LDRD_FALSE,
@@ -1896,6 +1902,7 @@ const struct tune_params arm_v6t2_tune =
5, /* Max cond insns. */
8, /* Memset max inline. */
1, /* Issue rate. */
+ 32, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_FALSE,
tune_params::PREF_LDRD_FALSE,
@@ -1920,6 +1927,7 @@ const struct tune_params arm_cortex_tune =
5, /* Max cond insns. */
8, /* Memset max inline. */
2, /* Issue rate. */
+ 64, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_FALSE,
tune_params::PREF_LDRD_FALSE,
@@ -1942,6 +1950,7 @@ const struct tune_params arm_cortex_a8_tune =
5, /* Max cond insns. */
8, /* Memset max inline. */
2, /* Issue rate. */
+ 64, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_FALSE,
tune_params::PREF_LDRD_FALSE,
@@ -1964,6 +1973,7 @@ const struct tune_params arm_cortex_a7_tune =
5, /* Max cond insns. */
8, /* Memset max inline. */
2, /* Issue rate. */
+ 64, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_FALSE,
tune_params::PREF_LDRD_FALSE,
@@ -1986,6 +1996,7 @@ const struct tune_params arm_cortex_a15_tune =
2, /* Max cond insns. */
8, /* Memset max inline. */
3, /* Issue rate. */
+ 64, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_FALSE,
tune_params::PREF_LDRD_TRUE,
@@ -2008,6 +2019,7 @@ const struct tune_params arm_cortex_a35_tune =
5, /* Max cond insns. */
8, /* Memset max inline. */
1, /* Issue rate. */
+ 64, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_FALSE,
tune_params::PREF_LDRD_FALSE,
@@ -2030,6 +2042,7 @@ const struct tune_params arm_cortex_a53_tune =
5, /* Max cond insns. */
8, /* Memset max inline. */
2, /* Issue rate. */
+ 64, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_FALSE,
tune_params::PREF_LDRD_FALSE,
@@ -2052,6 +2065,7 @@ const struct tune_params arm_cortex_a57_tune =
2, /* Max cond insns. */
8, /* Memset max inline. */
3, /* Issue rate. */
+ 64, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_FALSE,
tune_params::PREF_LDRD_TRUE,
@@ -2074,6 +2088,7 @@ const struct tune_params arm_exynosm1_tune =
2, /* Max cond insns. */
8, /* Memset max inline. */
3, /* Issue rate. */
+ 64, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_FALSE,
tune_params::PREF_LDRD_TRUE,
@@ -2096,6 +2111,7 @@ const struct tune_params arm_xgene1_tune =
2, /* Max cond insns. */
32, /* Memset max inline. */
4, /* Issue rate. */
+ 64, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_FALSE,
tune_params::PREF_LDRD_TRUE,
@@ -2121,6 +2137,7 @@ const struct tune_params arm_cortex_a5_tune =
1, /* Max cond insns. */
8, /* Memset max inline. */
2, /* Issue rate. */
+ 64, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_FALSE,
tune_params::PREF_LDRD_FALSE,
@@ -2143,6 +2160,7 @@ const struct tune_params arm_cortex_a9_tune =
5, /* Max cond insns. */
8, /* Memset max inline. */
2, /* Issue rate. */
+ 64, /* Bus width. */
ARM_PREFETCH_BENEFICIAL(4,32,32),
tune_params::PREF_CONST_POOL_FALSE,
tune_params::PREF_LDRD_FALSE,
@@ -2165,6 +2183,7 @@ const struct tune_params arm_cortex_a12_tune =
2, /* Max cond insns. */
8, /* Memset max inline. */
2, /* Issue rate. */
+ 64, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_FALSE,
tune_params::PREF_LDRD_TRUE,
@@ -2187,6 +2206,7 @@ const struct tune_params arm_cortex_a73_tune =
2, /* Max cond insns. */
8, /* Memset max inline. */
2, /* Issue rate. */
+ 64, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_FALSE,
tune_params::PREF_LDRD_TRUE,
@@ -2216,6 +2236,7 @@ const struct tune_params arm_v7m_tune =
2, /* Max cond insns. */
8, /* Memset max inline. */
1, /* Issue rate. */
+ 32, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_TRUE,
tune_params::PREF_LDRD_FALSE,
@@ -2240,6 +2261,7 @@ const struct tune_params arm_cortex_m7_tune =
1, /* Max cond insns. */
8, /* Memset max inline. */
2, /* Issue rate. */
+ 64, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_TRUE,
tune_params::PREF_LDRD_FALSE,
@@ -2265,6 +2287,7 @@ const struct tune_params arm_v6m_tune =
5, /* Max cond insns. */
8, /* Memset max inline. */
1, /* Issue rate. */
+ 32, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_FALSE,
tune_params::PREF_LDRD_FALSE,
@@ -2287,6 +2310,7 @@ const struct tune_params arm_fa726te_tune =
5, /* Max cond insns. */
8, /* Memset max inline. */
2, /* Issue rate. */
+ 32, /* Bus width. */
ARM_PREFETCH_NOT_BENEFICIAL,
tune_params::PREF_CONST_POOL_TRUE,
tune_params::PREF_LDRD_FALSE,
--
2.7.4
