On Mon, 2017-06-12 at 14:09 -0400, Michael Meissner wrote:
> >
> > > > +(define_insn "vsx_xvcvsxwsp"
> > > > + [(set (match_operand:V4SF 0 "vsx_register_operand" "=v")
> > > > + (unspec:V4SF[(match_operand:V4SI 1 "vsx_register_operand" "v")]
> > > > + UNSPEC_VSX_CVSXWSP))]
> > > > + "VECTOR_UNIT_VSX_P (V4SFmode)"
> > > > + "xvcvsxwsp %x0,%x1"
> > > > + [(set_attr "type" "vecdouble")])
> > >
> > > "v" is only the VRs... Do you want "wa" or similar instead?
> > >
> >
> > I went back and re-studied the Power register constrains. I find them a
> > bit confusing, I am sure they are perfectly clear to everyone else. So
> > the instructions all take VSX registers so "wa" should be fine if I
> > understand it correctly. Not sure there is any need to further
> > constrain with "vs" for doubles or "ww" but I think you could.
>
> Well in the power7 days, it wasn't clear whether we wanted to reduce the
> register set, so I added the general "wa", and then added the more specific
> changes ("ws", "wf", "wd"). In hindsight it probably wasn't a good idea. But
> the trouble is we can't delete the old constraints, or we would break user asm
> code.
>
> Over time, I have been deleting things where you have the specific constraint
> and the general one where I'm modifying code:
>
> (match_operand:V2DF 0 "=wd,?wa")
>
> to
>
> (match_operand:V2DF 0 "=wa")
>
> Now the second round of constraints are needed because of the
> -mupper-regs-<xxx> debug switches. You might/might not allow DFmode into the
> Altivec registers, and so you need several constraints:
>
> d Just the traditional FPRs
> ws Any FPR/Altivec register DFmode can go in for ISA 2.06 insns
> wk Like ws, but only if 64-bit direct moves are supported
> wv Only altivec registers (used for 64-bit load/stores)
>
> Note, you have to be careful not to allow a register constraint that the
> current type cannot go into. This is due to a 'feature' in the LRA register
> allocator that it will trap if such a case occurs. For example, for ISA 2.06,
> we do not have 32-bit floating point instructions in the Altivec registers.
> This means you can't use "v" (just the Altivec registers) on any code where
> -mcpu=power7 (or -mno-upper-regs-sf) is allowed.
>
Michael:
OK, so sounds like I should stick to the general wa register constraint.
The third field of the define_expand I have what I believe is called the
"condition string" as "TARGET_VSX". Is that the appropriate condition
string? I see conditions string "VECTOR_UNIT_VSX_P (V4SFmode)" also
used. Segher is thinking that this string would have the same effect as
"TARGET_VSX"?? How does one select the correct condition string based
on the register constraint?
Here is what I currently have for my define_expand. Is it correct?
;; Generate
float2
;; convert two long long signed ints to float
(define_expand "float2_v2di"
[(match_operand:V4SF 0 "register_operand" "=wa")
(unspec:V4SI [(match_operand:V2DI 1 "register_operand" "wa")
(match_operand:V2DI 2 "register_operand" "wa")]
UNSPEC_VSX_FLOAT2)]
"TARGET_VSX"
{
rtx rtx_src1, rtx_src2, rtx_dst;
rtx_dst = operands[0];
rtx_src1 = operands[1];
rtx_src2 = operands[2];
rs6000_generate_float2_code (true, rtx_dst, rtx_src1, rtx_src2);
DONE;
})
Thanks for your help on this.
