Hi Richard,
This is regarding the implementation of auto-vectorization based on my talk
titled "Improving the effectiveness and generality of GCC auto-vectorization"
in GNU Tools Cauldron 2015.
I have applied previous patches in branch 'unified-autovect' which generates
primitive reorder tree (PRT) for load/store operations, and performs few
optimizations to ensure optimal PRT is available for pattern matching. The
options to enable unified auto-vectorization are '-ftree-vectorize
-fopt-info-vec-all=file.txt -O2 -ftree-loop-vectorize-unified'.
Now I am working on pattern matcher for PRT using bottom up rewrite parsing
system (BURS) as described in "BURS Automata Generation" by Todd Proebsting.
The paper describes an algorithm to generate BURS transition tables for cost
effective pattern matching of complex target instructions. It takes target
instructions represented in context free grammar in normal form as input, and
generates transition table at build time of the compiler.
We have divided this problem into 3 parts:
1. Grammar creation for permute instructions of desired target at build time.
2. Transition table generation, and compile time executable code generation at
build time.
3. Pattern matching code at compile time.
The patch I have attached addresses 1st part.
As number of states in automata increase exponentially for operators to be
supported, I wanted to restrict the operators under consideration for BURS
automata to be generated. As scalar to vector translator for arithmetic and
logical instructions is already in place in GCC, and those operands do not play
any role in permute order creation, the BURS is generated only for permute
operators. For all other operators, GCC's current framework is to be used for
code generation.
Hence, the only operators that are supported by the automata are
ILV_2 : Interleave contents of 2 registers of size x and generate register of
size 2x.
EXTR_2,0 : Extract even elements from register of size x and generate
register of size x/2
EXTR_2,1 : Extract odd elements from register of size x and generate register
of size x/2
Also, the number of states also depend upon the leaves in grammar. Hence, we
are restricting the grammar to have 3 leaves namely REG, MEM and CONST.
We have defined new macro TARGET_VEC_PERM_CONST_ORDER which takes target
supported permute orders as input in struct vec_perm_order_spec.
Current patch constructs instruction tiles for the target from this macro and
optimizes those tiles using k-arity promotion reduction and redundancy
elimination to have optimal PRT per instruction. It then generates context free
grammar in normal form which can then be accepted by BURS algorithm to
construct transition table.
There are multiple issues that need to be handled to support permute
instructions across all architectures:
1. Constraints on input/output operands : We allow permutations on memory as
well as registers to allow strided load/store and register permutes.
2. Different vector sizes supported : Each vector size needs to be enlisted in
the macro in order to add support for that vector type.
3. Conditions under which the instruction is available : Like the condition
field in RTL in md patterns.
4. Arity of permute operation : Multiple input single output model is supported.
5. Default rules to be generated for grammar to be complete : We need to
identify default rules that are to be generated for pattern matcher so that the
grammar will be complete. We have added
goal --> reg
goal --> mem
reg --> mem
reg --> const
mem --> reg
mem --> const
:
:
reg_32 --> REG
reg_16 --> REG
reg_8 --> REG
reg_4 --> REG
reg_2 --> REG
reg -> reg_2
reg -> reg_4
reg -> reg_8
reg -> reg_16
reg -> reg_32
:
:
mem --> MEM
const --> CONST
reg --> EXTR_2,0 (reg)
reg --> EXTR_2,1 (reg)
reg --> ILV (reg, reg)
As we create 1 instruction tile per permute order in
TARGET_VEC_PERM_CONST_ORDER, more detailed the macro, more accurate the
pattern matcher becomes.
Interestingly, even though different entries are created for different vector
sizes, as and when possible, single tile is created for all vector sizes.
eg: In generated file insn-vect-inst-tiles.h which I have attached as sample,
tile for permute order
permute order - 0 16 2 18 4 20 6 22 8 24 10 26 12 28 14 30
ILV_2 (
EXTR_2,0 (PHR:0) ,
EXTR_2,0 (PHR:1))
is same as that for
permute order - 0 8 2 10 4 12 6 14
ILV_2 (
EXTR_2,0 (PHR:0) ,
EXTR_2,0 (PHR:1))
This can be useful for SVE like extensions where vector size can be dynamic.
Richard, can you please see if this looks correct, or do I need additional
information to successfully generate pattern matcher automatically?
Also, can you please comment on usability or scalability of this approach
across all the architectures or point me to appropriate people in the group
with whom I can discuss target specific vectorization issues?
- Thanks and regards,
Sameera D.Index: gcc/Makefile.in
===================================================================
--- gcc/Makefile.in (revision 246613)
+++ gcc/Makefile.in (working copy)
@@ -1067,7 +1067,12 @@
build/print-rtl.o build/hash-table.o
BUILD_MD = build/read-md.o
BUILD_ERRORS = build/errors.o
+BUILD_UNITED = build/vec.o build/hash-table.o build/errors.o \
+ build/ggc-none.o \
+ build/tree-vect-unified-common.o build/tree-vect-unified-opts.o
+build/tree-vect-unified-common.o : tree-vect-unified-common.c gtype-desc.h insn-codes.h
+build/tree-vect-unified-opts.o : tree-vect-unified-opts.c gtype-desc.h insn-codes.h
# Specify the directories to be searched for header files.
# Both . and srcdir are used, in that order,
# so that *config.h will be found in the compilation
@@ -2207,7 +2212,7 @@
insn-emit.c insn-recog.c insn-extract.c insn-output.c insn-peep.c \
insn-attr.h insn-attr-common.h insn-attrtab.c insn-dfatab.c \
insn-latencytab.c insn-preds.c gimple-match.c generic-match.c \
- insn-target-def.h
+ insn-target-def.h insn-vect-inst-tiles.h
# Dependencies for the md file. The first time through, we just assume
# the md file itself and the generated dependency file (in order to get
@@ -2234,7 +2239,8 @@
insn-extract.c insn-output.c \
insn-peep.c insn-recog.c
-simple_generated_h = $(simple_rtl_generated_h) insn-constants.h
+simple_generated_h = $(simple_rtl_generated_h) insn-constants.h \
+ insn-vect-inst-tiles.h
simple_generated_c = $(simple_rtl_generated_c) insn-enums.c
@@ -2602,6 +2608,8 @@
$(GENSUPPORT_H)
build/rtl.o: rtl.c $(BCONFIG_H) coretypes.h $(GTM_H) $(SYSTEM_H) \
$(RTL_H) $(GGC_H) errors.h
+build/tree.o: tree.c $(BCONFIG_H) coretypes.h $(GTM_H) $(SYSTEM_H) \
+ $(RTL_H) $(GGC_H) errors.h
build/vec.o : vec.c $(BCONFIG_H) $(SYSTEM_H) coretypes.h $(VEC_H) \
$(GGC_H) toplev.h $(DIAGNOSTIC_CORE_H)
build/hash-table.o : hash-table.c $(BCONFIG_H) $(SYSTEM_H) coretypes.h \
@@ -2655,6 +2663,9 @@
coretypes.h $(GTM_H) $(RTL_BASE_H) errors.h $(READ_MD_H) $(GENSUPPORT_H) \
$(HASH_TABLE_H) target-insns.def
build/gengenrtl.o : gengenrtl.c $(BCONFIG_H) $(SYSTEM_H) rtl.def
+build/genvect-inst-tiles.o : genvect-inst-tiles.c $(RTL_BASE_H) $(BCONFIG_H) \
+ $(SYSTEM_H) coretypes.h $(GTM_H) errors.h tree-vect-unified.h \
+ tree-vect-unified-opts.o tree-vect-unified-common.o
# The gengtype generator program is special: Two versions are built.
# One is for the build machine, and one is for the host to allow
@@ -2732,8 +2743,11 @@
genprogerr = $(genprogmd) genrtl modes gtype hooks cfn-macros
$(genprogerr:%=build/gen%$(build_exeext)): $(BUILD_ERRORS)
+genprogunited = vect-inst-tiles
+$(genprogunited:%=build/gen%$(build_exeext)): $(BUILD_UNITED)
+
# Remaining build programs.
-genprog = $(genprogerr) check checksum condmd match
+genprog = $(genprogerr) $(genprogunited) check checksum condmd match
# These programs need libs over and above what they get from the above list.
build/genautomata$(build_exeext) : BUILD_LIBS += -lm
Index: gcc/config/mips/mips.h
===================================================================
--- gcc/config/mips/mips.h (revision 246613)
+++ gcc/config/mips/mips.h (working copy)
@@ -3468,4 +3468,37 @@
(TARGET_LOAD_STORE_PAIRS && (TUNE_P5600 || TUNE_I6400) \
&& !TARGET_MICROMIPS && !TARGET_FIX_24K)
+#define TARGET_VEC_PERM_CONST_ORDER \
+{ \
+ {2, 2, 2, (int[2]){0,2}, 1, "PCKEV.D", "RRR", NULL, NULL}, \
+ {2, 2, 2, (int[2]){1,3}, 1, "PCKOD.D", "RRR", NULL, NULL}, \
+\
+ {2, 4, 4, (int[4]){0,4,2,6}, 1, "ILVEV.W", "RRR", NULL, NULL}, \
+ {2, 4, 4, (int[4]){1,5,3,7}, 1, "ILVOD.W", "RRR", NULL, NULL}, \
+ {2, 4, 4, (int[4]){0,2,4,6}, 1, "PCKEV.W", "RRR", NULL, NULL}, \
+ {2, 4, 4, (int[4]){1,3,5,7}, 1, "PCKOD.W", "RRR", NULL, NULL}, \
+ {2, 4, 4, (int[4]){2,6,3,7}, 1, "ILVL.W", "RRR", NULL, NULL}, \
+ {2, 4, 4, (int[4]){0,4,1,5}, 1, "ILVR.W", "RRR", NULL, NULL}, \
+\
+ {2, 8, 8, (int[8]){0,8,2,10,4,12,6,14}, 1, "ILVEV.H", "RRR", NULL, NULL}, \
+ {2, 8, 8, (int[8]){1,9,3,11,5,13,7,15}, 1, "ILVOD.H", "RRR", NULL, NULL}, \
+ {2, 8, 8, (int[8]){0,2,4,6,8,10,12,14}, 1, "PCKEV.H", "RRR", NULL, NULL}, \
+ {2, 8, 8, (int[8]){1,3,5,7,9,11,13,15}, 1, "PCKOD.H", "RRR", NULL, NULL}, \
+ {2, 8, 8, (int[8]){0,8,1,9,2,10,3,11}, 1, "ILVR.H", "RRR", NULL, NULL}, \
+ {2, 8, 8, (int[8]){4,12,5,13,6,14,7,15}, 1, "ILVL.H", "RRR", NULL, NULL}, \
+\
+ {2, 16, 16, (int[16]){0,16,2,18,4,20,6,22,8,24,10,26,12,28,14,30}, 1, \
+ "ILVEV.Q", "RRR", NULL, NULL}, \
+ {2, 16, 16, (int[16]){1,17,3,19,5,21,7,23,9,25,11,27,13,29,15,31}, 1, \
+ "ILVOD.Q", "RRR", NULL, NULL}, \
+ {2, 16, 16, (int[16]){0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30}, 1, \
+ "PCKEV.Q", "RRR", NULL, NULL}, \
+ {2, 16, 16, (int[16]){1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31}, 1, \
+ "PCKOD.Q", "RRR", NULL, NULL}, \
+ {2, 16, 16, (int[16]){8,24,9,25,10,26,11,27,12,28,13,29,14,30,15,31}, 1, \
+ "ILVL.Q", "RRR", NULL, NULL}, \
+ {2, 16, 16, (int[16]){0,16,1,17,2,18,3,19,4,20,5,21,6,22,7,23}, 1, \
+ "ILVR.Q", "RRR", NULL, NULL}, \
+}
+
#define MAX_VECTOR_SIZE 16
Index: gcc/coretypes.h
===================================================================
--- gcc/coretypes.h (revision 246613)
+++ gcc/coretypes.h (working copy)
@@ -358,6 +358,8 @@
typedef unsigned char uchar;
#endif
+struct vec_perm_order_spec;
+
/* Most host source files will require the following headers. */
#if !defined (GENERATOR_FILE) && !defined (USED_FOR_TARGET)
#include "machmode.h"
Index: gcc/genvect-inst-tiles.c
===================================================================
--- gcc/genvect-inst-tiles.c (revision 0)
+++ gcc/genvect-inst-tiles.c (working copy)
@@ -0,0 +1,713 @@
+/* Loop Vectorization using unified representation for permute instructions.
+ Copyright (C) 2003-2015 Free Software Foundation, Inc.
+ Contributed by Sameera Deshpande <sameera.deshpa...@imgtec.com>
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#define GENERATOR_FILE 1
+#include "bconfig.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "errors.h"
+#ifdef GENERATOR_FILE
+#include "machmode.h"
+#include "signop.h"
+#include "wide-int.h"
+#include "double-int.h"
+#include "real.h"
+#include "fixed-value.h"
+#include "statistics.h"
+#include "vec.h"
+#include "hash-table.h"
+#include "hash-set.h"
+#include "input.h"
+#include "is-a.h"
+#include "target.h"
+#endif
+
+#include "tree-core.h"
+#include "tree-vect-unified.h"
+//#include "tree-vect-unified-common.c"
+//#include "tree-vect-unified-opts.c"
+
+#define DEBUG 0
+int target_flags;
+
+struct vec_perm_order_spec target_spec[] = TARGET_VEC_PERM_CONST_ORDER;
+vec <struct grammar_rule *> rules;
+
+/* List of non-terminals used in grammar. The index is used in the grammar rule
+ to point to appropriate non-terminal in the list. For now, the non-terminal
+ is just list of strings with NT names. However if needed, it can be updated
+ to hold additional information in the structure. */
+vec<char *> non_terminals;
+
+/* List of terminals in Grammar. Currently, we support only 3 categories in
+ terminals -
+ MEM, REG and CONST. */
+vec<char *>terminals;
+
+/* Function create_placeholder.
+
+*/
+
+struct primop_tree *
+create_placeholder (int idx, char ch, struct primop_tree *parent)
+{
+ struct primop_tree *ptree;
+
+ ptree = populate_prim_node (POP_PH, NULL,
+ parent, NULL);
+ PT_PH_IDX (ptree) = idx;
+ PT_PH_TYPE (ptree) = ch;
+ return ptree;
+}
+
+/* Function create_perm_order_tree.
+
+ For each element in TARGET_VEC_PERM_CONST_ORDER
+ Do
+ 1. Create ILV node with arity out_vec_size.
+ 2. For ith element in perm_order
+ Do
+ 1. Create EXTR node with parts = in_vec_size and selector = i % parts
+ 2. Create child of EXTR as PLACEHOLDER_<M|C|R>_<i / parts>, i / parts
+ should not exceed num_opd. For k_arity_promotion_reduction and
+ unity_redundancy_elimination, PLACEHOLDER_<M|C|R>_<num> is used for
+ matching. Whereas for grammar definition, only PLACEHOLDER_<M|C|R>
+ is used for generating rules.
+ Done
+ Done
+*/
+
+struct primop_tree *
+create_perm_order_tree (struct vec_perm_order_spec spec)
+{
+ int i, num;
+ struct primop_tree *ilv_node, *expr_node, *placeholder;
+
+ ilv_node = create_primTree_combine (POP_ILV, NULL,
+ spec.out_vec_size, NULL, NULL);
+
+ for (i = 0; i < spec.out_vec_size; i++)
+ {
+ expr_node = create_primTree_partition (POP_EXTR, NULL,
+ spec.in_vec_size, spec.perm_order[i] % spec.in_vec_size,
+ NULL, ilv_node);
+ num = spec.perm_order[i] / spec.in_vec_size;
+ placeholder = create_placeholder (num,
+ spec.opd_constraint[num], expr_node);
+ add_child_at_index (expr_node, placeholder, 0);
+ add_child_at_index (ilv_node, expr_node, i);
+ }
+
+ return ilv_node;
+}
+
+/* Function print_perm_order.
+
+*/
+
+void print_perm_order (int *perm_order, int num)
+{
+ int i;
+
+ for (i = 0; i < num; i++)
+ printf (" %d ", perm_order[i]);
+}
+
+/* Function print_instruction_tile.
+
+*/
+
+void
+print_instruction_tile (struct primop_tree *ptree, int tab = 0)
+{
+ int i;
+
+ if (PT_NODE_OP (ptree) != POP_PH)
+ {
+ printf ("\n");
+ for (i = 0; i < tab; i++)
+ printf (" ");
+ }
+ switch (PT_NODE_OP (ptree))
+ {
+ case POP_EXTR:
+ printf ("EXTR_%d,%d (", PT_DIVISION (ptree),
+ PT_OPERAND_SELECTOR (ptree));
+ print_instruction_tile (PT_CHILD (ptree, 0), tab + 2);
+ printf (")");
+ break;
+ case POP_ILV:
+ printf ("ILV_%d (", PT_DIVISION (ptree));
+ for (i = 0; i < PT_DIVISION (ptree) - 1; i++)
+ {
+ print_instruction_tile (PT_CHILD (ptree, i), tab + 2);
+ printf (" , ");
+ }
+ print_instruction_tile (PT_CHILD (ptree, i), tab + 2);
+ printf (")");
+ break;
+ case POP_PH:
+ printf ("PH%c:%d", PT_PH_TYPE (ptree), PT_PH_IDX (ptree));
+ break;
+ default:
+ gcc_assert (!"\nUndesired case in printing tree.\n");
+ return;
+ }
+}
+
+/* Function print_instruction_tiles.
+
+*/
+
+void
+print_instruction_tiles ()
+{
+ int i;
+ printf ("/*");
+ for (i = 0; i < sizeof (target_spec)/sizeof (struct vec_perm_order_spec); i++)
+ {
+ printf ("\n\npermute order - ");
+ print_perm_order (target_spec[i].perm_order, target_spec[i].out_vec_size);
+ print_instruction_tile (target_spec[i].ptree);
+ }
+ printf ("*/");
+}
+
+/* Function create_instruction_tiles.
+
+ For each permute_order in TARGET_VEC_PERM_CONST_ORDER
+ Do
+ 1. Create permute order tree from permute order - the permute order tree
+ so created is of arity out_vec_size.
+ 2. Perform k_arity_promotion_reduction on permute order tree to reduce the
+ arity to 2. As out_vec_size is power of 2, the promotion/reduction is
+ never going to fail.
+ 3. Perform unity_redundancy_elimination of kind
+ ILV_m (EXTR_0(S), EXTR_1(S),...EXTR_m-1(S)) => S
+ EXTR_m,x (ILV_M(S1, S2, ... Sm)) => Sx
+ to get optimal permute order tree.
+ Done
+*/
+
+void
+create_instruction_tiles ()
+{
+ int i;
+ struct primop_tree *ptree;
+
+ for (i = 0; i < sizeof (target_spec)/sizeof (struct vec_perm_order_spec); i++)
+ {
+ ptree = create_perm_order_tree (target_spec[i]);
+ ptree = k_arity_promotion_reduction (ptree, 2);
+ ptree = unity_redundancy_elimination (ptree);
+ target_spec[i].ptree = ptree;
+ }
+
+}
+
+/* Function get_index.
+
+ Return index of non-terminal.
+*/
+
+int
+get_index (vec<char *> *worklist, char *str)
+{
+ int i;
+ for (i = 0; i < worklist->length (); i++)
+ {
+ if (!strcmp ((*worklist)[i], str))
+ return i;
+ }
+ return -1;
+}
+
+/* Function create_non_terminal.
+
+*/
+
+int
+create_non_terminal (char *str)
+{
+ int idx;
+ char *buf;
+
+ idx = get_index (&non_terminals, str);
+ if (idx != -1)
+ return idx;
+
+ idx = non_terminals.length ();
+ buf = (char *) xcalloc (strlen (str), sizeof (char));
+ strcpy (buf, str);
+ non_terminals.safe_insert (idx, buf);
+ return idx;
+}
+
+/* Function create_rule_NT_to_NT.
+
+ Creates grammar rule of kind NT --> NT for normalized grammar.
+*/
+
+struct grammar_rule *
+create_rule_NT_to_NT (int lhs_nt, int rhs_nt, int off)
+{
+ struct grammar_rule * rule;
+
+ rule = (struct grammar_rule *) xcalloc (1, sizeof (struct grammar_rule));
+ rule->lhs_nt = lhs_nt;
+ rule->type = NT2NT;
+ rule->u.non_terminal = rhs_nt;
+ rule->spec_idx = off;
+
+ return rule;
+}
+
+/* Function create_rule_NT_to_T.
+
+ Creates grammar rule of kind NT --> T for normalized grammar.
+*/
+
+struct grammar_rule *
+create_rule_NT_to_T (int lhs_nt, int rhs_t, int off)
+{
+ struct grammar_rule * rule;
+
+ rule = (struct grammar_rule *) xcalloc (1, sizeof (struct grammar_rule));
+ rule->lhs_nt = lhs_nt;
+ rule->type = NT2T;
+ rule->u.terminal = rhs_t;
+ rule->spec_idx = off;
+
+ return rule;
+}
+
+/* Function create_rule_NT_to_op_tree.
+
+ Creates grammar rule of kind NT --> OP (NT1, NT2 ...) for normalized grammar.
+*/
+
+struct grammar_rule *
+create_rule_NT_to_op_tree (int lhs_nt, enum primop_code op, int selector,
+ int division, int *rhs_opd, int length, int off)
+{
+ struct grammar_rule * rule;
+ int i;
+
+ rule = (struct grammar_rule *) xcalloc (1, sizeof (struct grammar_rule));
+ rule->lhs_nt = lhs_nt;
+ rule->type = NT2OP;
+ rule->u.rhs_exp.primop.op = op;
+ rule->u.rhs_exp.primop.opd_selector = selector;
+ rule->u.rhs_exp.primop.division = division;
+ rule->u.rhs_exp.primop.var_stride = NULL;
+ rule->spec_idx = off;
+
+ for (i = 0; i < length; i++)
+ {
+ rule->u.rhs_exp.rhs_nt.safe_insert (i, rhs_opd[i]);
+ }
+
+ return rule;
+}
+
+/* Function create_terminals.
+
+*/
+
+void
+create_terminals ()
+{
+ char * buf;
+
+ buf = (char *) xcalloc (4, sizeof (char));
+ strcpy (buf, "MEM");
+ terminals.safe_insert (0, buf);
+
+ buf = (char *) xcalloc (4, sizeof (char));
+ strcpy (buf, "REG");
+ terminals.safe_insert (1, buf);
+
+ buf = (char *) xcalloc (6, sizeof (char));
+ strcpy (buf, "CONST");
+ terminals.safe_insert (2, buf);
+
+ return;
+}
+
+/* Function create_default_rules.
+
+ Default rules Costs
+ ================================
+ goal --> reg (0)
+ goal --> mem (0)
+ reg --> mem (10)
+ reg --> const (5)
+ mem --> reg (10)
+ mem --> const (8)
+ :
+ :
+ reg_32 --> REG (0)
+ reg_16 --> REG (0)
+ reg_8 --> REG (0)
+ reg_4 --> REG (0)
+ reg_2 --> REG (0)
+ reg -> reg_2 (0)
+ reg -> reg_4 (0)
+ reg -> reg_8 (0)
+ reg -> reg_16 (0)
+ reg -> reg_32 (0)
+ :
+ :
+ mem --> MEM (0)
+ const --> CONST (0)
+ reg --> EXTR_2,0 (reg) (1)
+ reg --> EXTR_2,1 (reg) (1)
+ reg --> ILV (reg, reg) (2)
+*/
+
+void
+create_default_rules ()
+{
+ int goal, reg, mem, consti;
+ int i, vec_size, max_vec_size, vector_sizes;
+ int v[2];
+
+ create_terminals ();
+ goal = create_non_terminal ("goal");
+ reg = create_non_terminal ("reg");
+ mem = create_non_terminal ("mem");
+ consti = create_non_terminal ("const");
+ rules.safe_insert (rules.length (), create_rule_NT_to_NT (goal, reg, -1));
+ rules.safe_insert (rules.length (), create_rule_NT_to_NT (goal, mem, -1));
+ rules.safe_insert (rules.length (), create_rule_NT_to_NT (reg, mem, -1));
+ rules.safe_insert (rules.length (), create_rule_NT_to_NT (reg, consti, -1));
+ rules.safe_insert (rules.length (), create_rule_NT_to_NT (mem, reg, -1));
+ rules.safe_insert (rules.length (), create_rule_NT_to_NT (mem, consti, -1));
+ rules.safe_insert (rules.length (), create_rule_NT_to_T (mem, 0, -1));
+ rules.safe_insert (rules.length (), create_rule_NT_to_T (consti, 2, -1));
+
+ v[0] = v[1] = reg;
+
+ /* For each vector type supported, add NT2T rule for
+ reg. */
+ vector_sizes = MAX_VECTOR_SIZE;
+ max_vec_size = 1 << floor_log2 (vector_sizes);
+ vec_size = max_vec_size;
+
+ for (i = 0; i < floor_log2 (max_vec_size); i++)
+ {
+ char buf[20];
+ int idx;
+
+ sprintf (buf, "reg_%d", vec_size);
+ vec_size = vec_size >> 1;
+ idx = create_non_terminal (buf);
+ rules.safe_insert (rules.length (), create_rule_NT_to_NT (reg, idx, -1));
+ rules.safe_insert (rules.length (), create_rule_NT_to_T (idx, 1, -1));
+ }
+ rules.safe_insert (rules.length (),
+ create_rule_NT_to_op_tree (reg, POP_EXTR, 0, 2, v, 1, -1));
+ rules.safe_insert (rules.length (),
+ create_rule_NT_to_op_tree (reg, POP_EXTR, 1, 2, v, 1, -1));
+ rules.safe_insert (rules.length (),
+ create_rule_NT_to_op_tree (reg, POP_ILV, -1, 2, v, 2, -1));
+ return;
+}
+
+/* Function lookup_NT2T_in_grammar.
+
+ Look-up similar rule in rule-list.
+*/
+
+int
+lookup_NT2T_in_grammar (vec <struct grammar_rule *> *rule,
+ char *nt_substr, int t_idx)
+{
+ int i;
+ for (i = 0; i < rule->length (); i++)
+ {
+ struct grammar_rule *r;
+ rule->iterate (i, &r);
+
+ if (r->u.terminal == t_idx
+ && (strstr (non_terminals[r->lhs_nt], nt_substr)))
+ return i;
+ }
+ return -1;
+}
+
+/* Function lookup_NT2OP_in_grammar.
+
+ Look-up rule matching operation OP and children in vector nt_list.
+*/
+
+int
+lookup_NT2OP_in_grammar (vec <struct grammar_rule *> *rule,
+ enum primop_code code, int sel, int div,
+ int *nt_list, int length)
+{
+ int i, j;
+
+ for (i = 0; i < rule->length (); i++)
+ {
+ struct grammar_rule *r;
+ rule->iterate (i, &r);
+
+ if (r->u.rhs_exp.primop.op == code
+ && sel == r->u.rhs_exp.primop.opd_selector
+ && div == r->u.rhs_exp.primop.division)
+ {
+ for (j = 0; j < length; j++)
+ {
+ if (nt_list[j] != r->u.rhs_exp.rhs_nt[j])
+ break;
+ }
+ if (j == length)
+ return i;
+ }
+ }
+
+ return -1;
+}
+
+/* Function create_rule_for_ptree.
+
+ Recursive function to create grammar rules in normal form.
+
+ If the leaf node with placeholder :
+ - check if the rule is already present.
+ If yes, return the previously created non-terminal
+ Otherwise, create new non-terminal for the place-holder, with appropriate
+ vector size, and create rules of the form
+ <new_nt> --> <REG|MEM|CONST>
+ <reg_<vecsize>|mem|const> --> <new_nt>
+
+ If non-leaf node,
+ - For each child of the node invoke the function recursively.
+ - Once all children are processed, check if the rule with current primop
+ and children is already present.
+ If yes, return previously created non-terminal for corresponding rule.
+ Otherwise, create non-terminal for out_vecsize and create rules of the
+ form
+ <new_nt> --> PRIMOP (<list of NTs corresponding to respective child>)
+ <reg_<vecsize>|mem|const> --> <new_nt>
+*/
+
+int
+create_rule_for_ptree (struct primop_tree *ptree, int spec_idx, int out_vecsize,
+ int in_vecsize, vec <struct grammar_rule *> *rule)
+{
+ static int name_idx = 0;
+ int chld_nt[30];
+ char buf[20], name[20];
+ int found;
+ int nt;
+ int new_in_vec_size;
+ int i;
+
+ if (PT_NODE_OP (ptree) == POP_PH)
+ {
+ found = lookup_NT2T_in_grammar (rule, "ph",
+ PT_PH_TYPE (ptree) == 'R' ? 1 :
+ PT_PH_TYPE (ptree) == 'M' ? 0 : 2);
+ if (found != -1)
+ {
+ return (*rule)[found]->lhs_nt;
+ }
+ else
+ {
+ sprintf (name, "ph%d", name_idx++);
+ nt = create_non_terminal (name);
+ rule->safe_insert (rule->length (),
+ create_rule_NT_to_T (nt,
+ PT_PH_TYPE (ptree) == 'R' ? 1 :
+ PT_PH_TYPE (ptree) == 'M' ? 0 : 2, spec_idx));
+
+ sprintf (buf, "reg_%d", in_vecsize);
+ rule->safe_insert (rule->length (),
+ create_rule_NT_to_NT (
+ PT_PH_TYPE (ptree) == 'R' ? create_non_terminal (buf) :
+ PT_PH_TYPE (ptree) == 'M'
+ ? create_non_terminal ("mem") :
+ create_non_terminal ("const"), nt, spec_idx));
+ return nt;
+ }
+
+ }
+
+ if (PT_NODE_OP (ptree) == POP_ILV)
+ new_in_vec_size = in_vecsize / PT_DIVISION (ptree);
+ if (PT_NODE_OP (ptree) == POP_EXTR)
+ new_in_vec_size = in_vecsize * PT_DIVISION (ptree);
+
+ for (i = 0; i < ptree->children.length (); i++)
+ {
+ chld_nt[i] = create_rule_for_ptree (PT_CHILD (ptree, i),
+ spec_idx, in_vecsize, new_in_vec_size, rule);
+ }
+
+
+ found = lookup_NT2OP_in_grammar (rule, (enum primop_code) PT_NODE_OP (ptree),
+ PT_OPERAND_SELECTOR (ptree),
+ PT_DIVISION (ptree), chld_nt, i);
+
+ if (found != -1)
+ {
+ return (*rule)[found]->lhs_nt;
+ }
+ else
+ {
+ /* Create new NT, and create rule NT_to_OP. */
+ sprintf (name, "inter%d", name_idx++);
+ nt = create_non_terminal (name);
+ rule->safe_insert (rule->length (),
+ create_rule_NT_to_op_tree (nt, (enum primop_code) PT_NODE_OP (ptree),
+ PT_OPERAND_SELECTOR (ptree), PT_DIVISION (ptree),
+ chld_nt, i, spec_idx));
+
+ sprintf (buf, "reg_%d", out_vecsize);
+ rule->safe_insert (rule->length (),
+ create_rule_NT_to_NT (
+ target_spec[spec_idx].opd_constraint[0] == 'R' ?
+ create_non_terminal (buf) :
+ target_spec[spec_idx].opd_constraint[0] == 'M' ?
+ create_non_terminal ("mem") :
+ create_non_terminal ("const"), nt, spec_idx));
+
+ return nt;
+ }
+}
+
+/* Function create_grammar_rules.
+
+ Creates grammar rules for each primop_tree.
+*/
+
+void
+create_grammar_rules ()
+{
+ int i, j, k;
+
+ create_default_rules ();
+ for (i = 0, j = rules.length ();
+ i < sizeof (target_spec)/sizeof (struct vec_perm_order_spec);
+ i++)
+ {
+ int idx = 0;
+ vec <struct grammar_rule *> rule = vNULL;
+
+ create_rule_for_ptree (target_spec[i].ptree, i,
+ target_spec[i].out_vec_size,
+ target_spec[i].in_vec_size, &rule);
+
+ for (k = 0; k < rule.length (); k++)
+ rules.safe_insert (j++, rule[k]);
+ }
+}
+
+/* Function print_rule_operands.
+
+*/
+
+void
+print_rule_operands (vec<int> *arr)
+{
+ int i;
+ printf ("%s", non_terminals[(*arr)[0]]);
+ for (i = 1; i < arr->length (); i++)
+ {
+ printf (", %s", non_terminals[(*arr)[i]]);
+ }
+}
+
+/* Function print_grammar_rule.
+
+*/
+
+void
+print_grammar_rule (struct grammar_rule *rule)
+{
+ switch (rule->type)
+ {
+ case NT2T:
+ printf ("%s --> %s\n", non_terminals[rule->lhs_nt],
+ terminals[rule->u.terminal]);
+ break;
+
+ case NT2NT:
+ printf ("%s --> %s\n", non_terminals[rule->lhs_nt],
+ non_terminals[rule->u.non_terminal]);
+
+ break;
+
+ case NT2OP:
+ printf ("%s --> ", non_terminals[rule->lhs_nt]);
+ switch (rule->u.rhs_exp.primop.op)
+ {
+ case POP_ILV:
+ printf ("ILV_%d (", rule->u.rhs_exp.primop.division);
+ break;
+ case POP_EXTR:
+ printf ("EXTR_%d,%d (", rule->u.rhs_exp.primop.division,
+ rule->u.rhs_exp.primop.opd_selector);
+ break;
+ default:
+ gcc_assert (0);
+ }
+ print_rule_operands (&rule->u.rhs_exp.rhs_nt);
+ printf (")\n");
+
+ break;
+
+ default:
+ gcc_assert (0);
+ }
+}
+
+/* Function print_grammar_rules.
+
+ Emit grammar rules for which automata is constructed.
+
+*/
+
+void
+print_grammar_rules ()
+{
+ int i;
+
+ printf ("/*\n");
+ for (i = 0; i < rules.length (); i++)
+ {
+ print_grammar_rule (rules[i]);
+ }
+ printf ("*/\n");
+}
+
+
+int main (int argc, const char **argv)
+{
+ printf ("/* Generated automatically by the program `genvect-inst-tiles'\n\
+from the macro TARGET_VEC_PERM_CONST_ORDER in target header file. */\n\n");
+ create_instruction_tiles ();
+ print_instruction_tiles ();
+ create_grammar_rules ();
+ print_grammar_rules ();
+}
Index: gcc/tree-vect-unified-common.c
===================================================================
--- gcc/tree-vect-unified-common.c (revision 246613)
+++ gcc/tree-vect-unified-common.c (working copy)
@@ -61,7 +61,6 @@
#include "builtins.h"
#include "params.h"
#include "pretty-print.h"
-#include "pretty-print.h"
#else
#include "errors.h"
#include "machmode.h"
@@ -78,9 +77,6 @@
#include "is-a.h"
#include "target.h"
#include "tree-core.h"
-#include "tree-vect-unified.h"
-
-
#endif
#include "tree-vect-unified.h"
Index: gcc/tree-vect-unified-opts.c
===================================================================
--- gcc/tree-vect-unified-opts.c (revision 246613)
+++ gcc/tree-vect-unified-opts.c (working copy)
@@ -61,7 +61,6 @@
#include "builtins.h"
#include "params.h"
#include "pretty-print.h"
-#include "pretty-print.h"
#else
# include "errors.h"
#include "machmode.h"
@@ -78,8 +77,6 @@
#include "is-a.h"
#include "target.h"
#include "tree-core.h"
-#include "tree-vect-unified.h"
-
#endif
#include "tree-vect-unified.h"
@@ -520,8 +517,8 @@
annotate_tree_nodes (struct primop_tree *ptree, int *end,
struct primop_tree **leaves)
{
- int key;
- long long int idx;
+ long long int key;
+ int idx;
int length = 0;
int i, j;
struct primop_tree *temp[150];
@@ -541,8 +538,8 @@
for (i = 0; i < ptree->children.length (); i++)
{
- key = (key | annotate_tree_nodes (PT_CHILD (ptree, i),
- &length, temp)) << 12;
+ key = (key << 12)
+ | annotate_tree_nodes (PT_CHILD (ptree, i), &length, temp);
for (j = 0; j < length; j++)
{
leaves[(*end)++] = temp[j];
@@ -575,7 +572,11 @@
bool changed = false;
int to_be_matched;
struct primop_tree *temp_ptree;
- int i;
+ int i, j;
+ long long int key;
+ int idx, end;
+ struct primop_tree *leaves[150];
+ struct primtree_hash_table *new_hash;
*new_ptree = ptree;
@@ -612,6 +613,8 @@
}
}
+ key = PT_NODE_OP (ptree) << 10;
+ end = 0;
for (i = 0; i < (*new_ptree)->children.length (); i++)
{
changed |= unity_redundancy_elimination_2 (PT_CHILD (*new_ptree, i),
@@ -618,8 +621,45 @@
&temp_ptree);
PT_CHILD (*new_ptree, i) = temp_ptree;
PT_PARENT (temp_ptree) = *new_ptree;
+ if (PT_NODE_OP (temp_ptree) == POP_MEMREF
+ || PT_NODE_OP (temp_ptree) == POP_PH
+ || PT_NODE_OP (temp_ptree) == POP_CONST)
+ {
+ key = (key | 0xfff) << 12;
+ leaves[end++] = temp_ptree;
+ }
+ else
+ {
+ key = (key << 12) | PT_AUX(temp_ptree);
+
+ for (j = 0;
+ j < primop_hash[PT_AUX(temp_ptree)]->leaves.length ();
+ j++)
+ {
+ leaves[end + j] = primop_hash[PT_AUX(temp_ptree)]->leaves[j];
+ }
+
+ end = end + j;
+ }
+
}
+ idx = lookup_key_in_table (key, leaves, end);
+
+ if (idx == -1)
+ {
+ // Create new entry.
+ new_hash = (struct primtree_hash_table *) xcalloc (1,
+ sizeof (struct primtree_hash_table));
+ new_hash->key = key;
+ new_hash->leaves = vNULL;
+ for (i = 0; i < end; i++)
+ new_hash->leaves.safe_insert (new_hash->leaves.length (), leaves[i]);
+ idx = primop_hash.length ();
+ primop_hash.safe_insert (idx, new_hash);
+ }
+ PT_AUX (*new_ptree) = idx;
+
return changed;
}
@@ -640,13 +680,12 @@
bool changed;
annotate_tree_nodes (ptree, &end, dummy);
-
changed = false;
do {
changed = unity_redundancy_elimination_2 (ptree, &new_ptree);
- if (ptree == new_ptree)
- break;
+ //if (ptree == new_ptree)
+ // break;
ptree = new_ptree;
} while (changed == true);
Index: gcc/tree-vect-unified.c
===================================================================
--- gcc/tree-vect-unified.c (revision 246613)
+++ gcc/tree-vect-unified.c (working copy)
@@ -2527,6 +2527,26 @@
dump_iter_node (tmp_iter_node, alt_dump_file);
}
+ worklist = vNULL;
+ worklist = (ITER_NODE_LOOP_BODY (tmp_iter_node)).copy ();
+ for (i = 0; i < worklist.length (); i++)
+ {
+ gcc_assert (worklist.iterate (i, &tmp_tree));
+ tmp_tree = unity_redundancy_elimination (tmp_tree);
+
+ ITER_NODE_LOOP_BODY (tmp_iter_node)[i] = tmp_tree;
+ }
+
+ if (dump_enabled_p ())
+ {
+ dump_printf (MSG_NOTE, "\nUnity redundancy elimination applied.\n");
+ if (dump_file)
+ dump_iter_node (tmp_iter_node, dump_file);
+ if (alt_dump_file)
+ dump_iter_node (tmp_iter_node, alt_dump_file);
+ }
+
+
gimple *loop_vectorized_call = vect_loop_vectorized_call (loop);
/* If the loop is vectorized, set uid of stmts within scalar loop to
0. This change is needed if transform phase uses this loop info. */
Index: gcc/tree-vect-unified.h
===================================================================
--- gcc/tree-vect-unified.h (revision 246613)
+++ gcc/tree-vect-unified.h (working copy)
@@ -285,6 +285,87 @@
#undef DEFTREECODE
#undef END_OF_BASE_TREE_CODES
+/* TARGET_VEC_PERM_CONST_ORDER - If defined, this target hook points to an array
+ of "struct vec_perm_order_spec" specifying various permute orders supported
+ by the target architecture. */
+
+struct vec_perm_order_spec
+{
+ /* Number of operands in permute order specified. */
+ int num_opd;
+
+ /* Vector size of input permute order. */
+ int in_vec_size;
+
+ /* Vector size of resultant permute order. It can be identified from the size
+ of perm_order, however, if by mistake, this field is not defined properly,
+ can lead to errors. Hence, taking that as input. */
+ int out_vec_size;
+
+ /* Permute order of operands. */
+ int *perm_order;
+
+ /* Cost of permute operation. */
+ int cost;
+
+ /* Name of permute operation for debugging purpose. */
+ char *op_name;
+
+ /* The constraints on input and output operands of this instruction.
+ Restricting these to R,M or I for register, memory and integer constant
+ respectively. This is needed for reduction rules to be generated for BURS
+ tree. It should have comma separated list - with num_opd + 1 listings. */
+ char * opd_constraint;
+
+ /* Condition under which the instruction can be emitted. Thinking of
+ something like condition part in define_insn. */
+ char * cond;
+
+ /* PRIMOP_TREE constructed after tile construction. */
+ struct primop_tree *ptree;
+};
+
+enum rule_type {NT2T, NT2NT, NT2OP};
+
+/* Normalized context free grammar of the form
+ NT --> T
+ NT--> NT
+ NT --> OP (<list of NTs>) */
+struct grammar_rule
+{
+ /* Pointer to vec_perm_order_spec corresponding to grammar rule. For default
+ rules, this value is NULL. */
+ struct vec_perm_order_spec *porder;
+
+ /* Non-terminal on LHS. */
+ int lhs_nt;
+
+ enum rule_type type;
+
+ int spec_idx;
+
+ union {
+ /* Terminal on RHS. */
+ int terminal;
+
+ /* Non-terminal on RHS. */
+ int non_terminal;
+
+ /* RHS of the form OP_div,sel (NT1, NT2...NTk) for k_arity operation op. */
+ struct rhs_expression {
+ struct operation {
+ enum primop_code op;
+ int opd_selector;
+ int division;
+ tree *var_stride;
+ } primop;
+
+ vec<int> rhs_nt;
+ } rhs_exp;
+ } u;
+};
+
+
extern unsigned int vectorize_loops_using_uniop (void);
extern struct primop_tree * analyze_and_create_ptree (struct primop_tree *,
gimple *, struct ITER_node *);
/* Generated automatically by the program `genvect-inst-tiles'
from the macro TARGET_VEC_PERM_CONST_ORDER in target header file. */
/*
permute order - 0 2
ILV_2 (
EXTR_2,0 (PHR:0) ,
EXTR_2,0 (PHR:1))
permute order - 1 3
ILV_2 (
EXTR_2,1 (PHR:0) ,
EXTR_2,1 (PHR:1))
permute order - 0 4 2 6
ILV_2 (
EXTR_2,0 (PHR:0) ,
EXTR_2,0 (PHR:1))
permute order - 1 5 3 7
ILV_2 (
EXTR_2,1 (PHR:0) ,
EXTR_2,1 (PHR:1))
permute order - 0 2 4 6
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (PHR:0)) ,
EXTR_2,0 (
EXTR_2,0 (PHR:1))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (PHR:0)) ,
EXTR_2,1 (
EXTR_2,0 (PHR:1))))
permute order - 1 3 5 7
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,1 (PHR:0)) ,
EXTR_2,0 (
EXTR_2,1 (PHR:1))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,1 (PHR:0)) ,
EXTR_2,1 (
EXTR_2,1 (PHR:1))))
permute order - 2 6 3 7
ILV_2 (
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (PHR:0)) ,
EXTR_2,1 (
EXTR_2,1 (PHR:0))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (PHR:1)) ,
EXTR_2,1 (
EXTR_2,1 (PHR:1))))
permute order - 0 4 1 5
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (PHR:0)) ,
EXTR_2,0 (
EXTR_2,1 (PHR:0))) ,
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (PHR:1)) ,
EXTR_2,0 (
EXTR_2,1 (PHR:1))))
permute order - 0 8 2 10 4 12 6 14
ILV_2 (
EXTR_2,0 (PHR:0) ,
EXTR_2,0 (PHR:1))
permute order - 1 9 3 11 5 13 7 15
ILV_2 (
EXTR_2,1 (PHR:0) ,
EXTR_2,1 (PHR:1))
permute order - 0 2 4 6 8 10 12 14
ILV_2 (
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (PHR:0))) ,
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (PHR:1)))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (PHR:0))) ,
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (PHR:1))))) ,
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (PHR:0))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (PHR:1)))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (PHR:0))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (PHR:1))))))
permute order - 1 3 5 7 9 11 13 15
ILV_2 (
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (PHR:0))) ,
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (PHR:1)))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (PHR:0))) ,
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (PHR:1))))) ,
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (PHR:0))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (PHR:1)))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (PHR:0))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (PHR:1))))))
permute order - 0 8 1 9 2 10 3 11
ILV_2 (
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (PHR:0))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (PHR:0)))) ,
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (PHR:0))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (PHR:0))))) ,
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (PHR:1))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (PHR:1)))) ,
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (PHR:1))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (PHR:1))))))
permute order - 4 12 5 13 6 14 7 15
ILV_2 (
ILV_2 (
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (PHR:0))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (PHR:0)))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (PHR:0))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (PHR:0))))) ,
ILV_2 (
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (PHR:1))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (PHR:1)))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (PHR:1))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (PHR:1))))))
permute order - 0 16 2 18 4 20 6 22 8 24 10 26 12 28 14 30
ILV_2 (
EXTR_2,0 (PHR:0) ,
EXTR_2,0 (PHR:1))
permute order - 1 17 3 19 5 21 7 23 9 25 11 27 13 29 15 31
ILV_2 (
EXTR_2,1 (PHR:0) ,
EXTR_2,1 (PHR:1))
permute order - 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
ILV_2 (
ILV_2 (
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (PHR:0)))) ,
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (PHR:1))))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (PHR:0)))) ,
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (PHR:1)))))) ,
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (PHR:0)))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (PHR:1))))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (PHR:0)))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (PHR:1))))))) ,
ILV_2 (
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (PHR:0)))) ,
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (PHR:1))))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (PHR:0)))) ,
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (PHR:1)))))) ,
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (PHR:0)))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (PHR:1))))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (PHR:0)))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (PHR:1))))))))
permute order - 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
ILV_2 (
ILV_2 (
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (PHR:0)))) ,
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (PHR:1))))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (PHR:0)))) ,
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (PHR:1)))))) ,
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (PHR:0)))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (PHR:1))))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (PHR:0)))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (PHR:1))))))) ,
ILV_2 (
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (PHR:0)))) ,
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (PHR:1))))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (PHR:0)))) ,
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (PHR:1)))))) ,
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (PHR:0)))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (PHR:1))))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (PHR:0)))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (PHR:1))))))))
permute order - 8 24 9 25 10 26 11 27 12 28 13 29 14 30 15 31
ILV_2 (
ILV_2 (
ILV_2 (
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (PHR:0)))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (PHR:0))))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (PHR:0)))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (PHR:0)))))) ,
ILV_2 (
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (PHR:0)))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (PHR:0))))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (PHR:0)))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (PHR:0))))))) ,
ILV_2 (
ILV_2 (
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (PHR:1)))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (PHR:1))))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (PHR:1)))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (PHR:1)))))) ,
ILV_2 (
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (PHR:1)))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (PHR:1))))) ,
ILV_2 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (PHR:1)))) ,
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (PHR:1))))))))
permute order - 0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23
ILV_2 (
ILV_2 (
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (PHR:0)))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (PHR:0))))) ,
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (PHR:0)))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (PHR:0)))))) ,
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (PHR:0)))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (PHR:0))))) ,
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (PHR:0)))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (PHR:0))))))) ,
ILV_2 (
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (PHR:1)))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,0 (PHR:1))))) ,
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (PHR:1)))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,0 (PHR:1)))))) ,
ILV_2 (
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (PHR:1)))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,0 (
EXTR_2,1 (PHR:1))))) ,
ILV_2 (
EXTR_2,0 (
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (PHR:1)))) ,
EXTR_2,0 (
EXTR_2,1 (
EXTR_2,1 (
EXTR_2,1 (PHR:1))))))))*//*
goal --> reg
goal --> mem
reg --> mem
reg --> const
mem --> reg
mem --> const
mem --> MEM
const --> CONST
reg --> reg_16
reg_16 --> REG
reg --> reg_8
reg_8 --> REG
reg --> reg_4
reg_4 --> REG
reg --> reg_2
reg_2 --> REG
reg --> EXTR_2,0 (reg)
reg --> EXTR_2,1 (reg)
reg --> ILV_2 (reg, reg)
ph0 --> REG
reg_2 --> ph0
inter1 --> EXTR_2,0 (ph0)
reg_2 --> inter1
inter2 --> ILV_2 (inter1, inter1)
reg_2 --> inter2
ph3 --> REG
reg_2 --> ph3
inter4 --> EXTR_2,1 (ph3)
reg_2 --> inter4
inter5 --> ILV_2 (inter4, inter4)
reg_2 --> inter5
ph6 --> REG
reg_4 --> ph6
inter7 --> EXTR_2,0 (ph6)
reg_4 --> inter7
inter8 --> ILV_2 (inter7, inter7)
reg_4 --> inter8
ph9 --> REG
reg_4 --> ph9
inter10 --> EXTR_2,1 (ph9)
reg_4 --> inter10
inter11 --> ILV_2 (inter10, inter10)
reg_4 --> inter11
ph12 --> REG
reg_4 --> ph12
inter13 --> EXTR_2,0 (ph12)
reg_1 --> inter13
inter14 --> EXTR_2,0 (inter13)
reg_2 --> inter14
inter15 --> ILV_2 (inter14, inter14)
reg_4 --> inter15
inter16 --> EXTR_2,1 (inter13)
reg_2 --> inter16
inter17 --> ILV_2 (inter16, inter16)
reg_4 --> inter17
inter18 --> ILV_2 (inter15, inter17)
reg_4 --> inter18
ph19 --> REG
reg_4 --> ph19
inter20 --> EXTR_2,1 (ph19)
reg_1 --> inter20
inter21 --> EXTR_2,0 (inter20)
reg_2 --> inter21
inter22 --> ILV_2 (inter21, inter21)
reg_4 --> inter22
inter23 --> EXTR_2,1 (inter20)
reg_2 --> inter23
inter24 --> ILV_2 (inter23, inter23)
reg_4 --> inter24
inter25 --> ILV_2 (inter22, inter24)
reg_4 --> inter25
ph26 --> REG
reg_4 --> ph26
inter27 --> EXTR_2,0 (ph26)
reg_1 --> inter27
inter28 --> EXTR_2,1 (inter27)
reg_2 --> inter28
inter29 --> EXTR_2,1 (ph26)
reg_1 --> inter29
inter30 --> EXTR_2,1 (inter29)
reg_2 --> inter30
inter31 --> ILV_2 (inter28, inter30)
reg_4 --> inter31
inter32 --> ILV_2 (inter31, inter31)
reg_4 --> inter32
ph33 --> REG
reg_4 --> ph33
inter34 --> EXTR_2,0 (ph33)
reg_1 --> inter34
inter35 --> EXTR_2,0 (inter34)
reg_2 --> inter35
inter36 --> EXTR_2,1 (ph33)
reg_1 --> inter36
inter37 --> EXTR_2,0 (inter36)
reg_2 --> inter37
inter38 --> ILV_2 (inter35, inter37)
reg_4 --> inter38
inter39 --> ILV_2 (inter38, inter38)
reg_4 --> inter39
ph40 --> REG
reg_8 --> ph40
inter41 --> EXTR_2,0 (ph40)
reg_8 --> inter41
inter42 --> ILV_2 (inter41, inter41)
reg_8 --> inter42
ph43 --> REG
reg_8 --> ph43
inter44 --> EXTR_2,1 (ph43)
reg_8 --> inter44
inter45 --> ILV_2 (inter44, inter44)
reg_8 --> inter45
ph46 --> REG
reg_8 --> ph46
inter47 --> EXTR_2,0 (ph46)
reg_2 --> inter47
inter48 --> EXTR_2,0 (inter47)
reg_1 --> inter48
inter49 --> EXTR_2,0 (inter48)
reg_2 --> inter49
inter50 --> ILV_2 (inter49, inter49)
reg_4 --> inter50
inter51 --> EXTR_2,1 (inter48)
reg_2 --> inter51
inter52 --> ILV_2 (inter51, inter51)
reg_4 --> inter52
inter53 --> ILV_2 (inter50, inter52)
reg_8 --> inter53
inter54 --> EXTR_2,1 (inter47)
reg_1 --> inter54
inter55 --> EXTR_2,0 (inter54)
reg_2 --> inter55
inter56 --> ILV_2 (inter55, inter55)
reg_4 --> inter56
inter57 --> EXTR_2,1 (inter54)
reg_2 --> inter57
inter58 --> ILV_2 (inter57, inter57)
reg_4 --> inter58
inter59 --> ILV_2 (inter56, inter58)
reg_8 --> inter59
inter60 --> ILV_2 (inter53, inter59)
reg_8 --> inter60
ph61 --> REG
reg_8 --> ph61
inter62 --> EXTR_2,1 (ph61)
reg_2 --> inter62
inter63 --> EXTR_2,0 (inter62)
reg_1 --> inter63
inter64 --> EXTR_2,0 (inter63)
reg_2 --> inter64
inter65 --> ILV_2 (inter64, inter64)
reg_4 --> inter65
inter66 --> EXTR_2,1 (inter63)
reg_2 --> inter66
inter67 --> ILV_2 (inter66, inter66)
reg_4 --> inter67
inter68 --> ILV_2 (inter65, inter67)
reg_8 --> inter68
inter69 --> EXTR_2,1 (inter62)
reg_1 --> inter69
inter70 --> EXTR_2,0 (inter69)
reg_2 --> inter70
inter71 --> ILV_2 (inter70, inter70)
reg_4 --> inter71
inter72 --> EXTR_2,1 (inter69)
reg_2 --> inter72
inter73 --> ILV_2 (inter72, inter72)
reg_4 --> inter73
inter74 --> ILV_2 (inter71, inter73)
reg_8 --> inter74
inter75 --> ILV_2 (inter68, inter74)
reg_8 --> inter75
ph76 --> REG
reg_8 --> ph76
inter77 --> EXTR_2,0 (ph76)
reg_2 --> inter77
inter78 --> EXTR_2,0 (inter77)
reg_1 --> inter78
inter79 --> EXTR_2,0 (inter78)
reg_2 --> inter79
inter80 --> EXTR_2,1 (inter77)
reg_1 --> inter80
inter81 --> EXTR_2,0 (inter80)
reg_2 --> inter81
inter82 --> ILV_2 (inter79, inter81)
reg_4 --> inter82
inter83 --> EXTR_2,1 (ph76)
reg_2 --> inter83
inter84 --> EXTR_2,0 (inter83)
reg_1 --> inter84
inter85 --> EXTR_2,0 (inter84)
reg_2 --> inter85
inter86 --> EXTR_2,1 (inter83)
reg_1 --> inter86
inter87 --> EXTR_2,0 (inter86)
reg_2 --> inter87
inter88 --> ILV_2 (inter85, inter87)
reg_4 --> inter88
inter89 --> ILV_2 (inter82, inter88)
reg_8 --> inter89
inter90 --> ILV_2 (inter89, inter89)
reg_8 --> inter90
ph91 --> REG
reg_8 --> ph91
inter92 --> EXTR_2,0 (ph91)
reg_2 --> inter92
inter93 --> EXTR_2,0 (inter92)
reg_1 --> inter93
inter94 --> EXTR_2,1 (inter93)
reg_2 --> inter94
inter95 --> EXTR_2,1 (inter92)
reg_1 --> inter95
inter96 --> EXTR_2,1 (inter95)
reg_2 --> inter96
inter97 --> ILV_2 (inter94, inter96)
reg_4 --> inter97
inter98 --> EXTR_2,1 (ph91)
reg_2 --> inter98
inter99 --> EXTR_2,0 (inter98)
reg_1 --> inter99
inter100 --> EXTR_2,1 (inter99)
reg_2 --> inter100
inter101 --> EXTR_2,1 (inter98)
reg_1 --> inter101
inter102 --> EXTR_2,1 (inter101)
reg_2 --> inter102
inter103 --> ILV_2 (inter100, inter102)
reg_4 --> inter103
inter104 --> ILV_2 (inter97, inter103)
reg_8 --> inter104
inter105 --> ILV_2 (inter104, inter104)
reg_8 --> inter105
ph106 --> REG
reg_16 --> ph106
inter107 --> EXTR_2,0 (ph106)
reg_16 --> inter107
inter108 --> ILV_2 (inter107, inter107)
reg_16 --> inter108
ph109 --> REG
reg_16 --> ph109
inter110 --> EXTR_2,1 (ph109)
reg_16 --> inter110
inter111 --> ILV_2 (inter110, inter110)
reg_16 --> inter111
ph112 --> REG
reg_16 --> ph112
inter113 --> EXTR_2,0 (ph112)
reg_4 --> inter113
inter114 --> EXTR_2,0 (inter113)
reg_2 --> inter114
inter115 --> EXTR_2,0 (inter114)
reg_1 --> inter115
inter116 --> EXTR_2,0 (inter115)
reg_2 --> inter116
inter117 --> ILV_2 (inter116, inter116)
reg_4 --> inter117
inter118 --> EXTR_2,1 (inter115)
reg_2 --> inter118
inter119 --> ILV_2 (inter118, inter118)
reg_4 --> inter119
inter120 --> ILV_2 (inter117, inter119)
reg_8 --> inter120
inter121 --> EXTR_2,1 (inter114)
reg_1 --> inter121
inter122 --> EXTR_2,0 (inter121)
reg_2 --> inter122
inter123 --> ILV_2 (inter122, inter122)
reg_4 --> inter123
inter124 --> EXTR_2,1 (inter121)
reg_2 --> inter124
inter125 --> ILV_2 (inter124, inter124)
reg_4 --> inter125
inter126 --> ILV_2 (inter123, inter125)
reg_8 --> inter126
inter127 --> ILV_2 (inter120, inter126)
reg_16 --> inter127
inter128 --> EXTR_2,1 (inter113)
reg_2 --> inter128
inter129 --> EXTR_2,0 (inter128)
reg_1 --> inter129
inter130 --> EXTR_2,0 (inter129)
reg_2 --> inter130
inter131 --> ILV_2 (inter130, inter130)
reg_4 --> inter131
inter132 --> EXTR_2,1 (inter129)
reg_2 --> inter132
inter133 --> ILV_2 (inter132, inter132)
reg_4 --> inter133
inter134 --> ILV_2 (inter131, inter133)
reg_8 --> inter134
inter135 --> EXTR_2,1 (inter128)
reg_1 --> inter135
inter136 --> EXTR_2,0 (inter135)
reg_2 --> inter136
inter137 --> ILV_2 (inter136, inter136)
reg_4 --> inter137
inter138 --> EXTR_2,1 (inter135)
reg_2 --> inter138
inter139 --> ILV_2 (inter138, inter138)
reg_4 --> inter139
inter140 --> ILV_2 (inter137, inter139)
reg_8 --> inter140
inter141 --> ILV_2 (inter134, inter140)
reg_16 --> inter141
inter142 --> ILV_2 (inter127, inter141)
reg_16 --> inter142
ph143 --> REG
reg_16 --> ph143
inter144 --> EXTR_2,1 (ph143)
reg_4 --> inter144
inter145 --> EXTR_2,0 (inter144)
reg_2 --> inter145
inter146 --> EXTR_2,0 (inter145)
reg_1 --> inter146
inter147 --> EXTR_2,0 (inter146)
reg_2 --> inter147
inter148 --> ILV_2 (inter147, inter147)
reg_4 --> inter148
inter149 --> EXTR_2,1 (inter146)
reg_2 --> inter149
inter150 --> ILV_2 (inter149, inter149)
reg_4 --> inter150
inter151 --> ILV_2 (inter148, inter150)
reg_8 --> inter151
inter152 --> EXTR_2,1 (inter145)
reg_1 --> inter152
inter153 --> EXTR_2,0 (inter152)
reg_2 --> inter153
inter154 --> ILV_2 (inter153, inter153)
reg_4 --> inter154
inter155 --> EXTR_2,1 (inter152)
reg_2 --> inter155
inter156 --> ILV_2 (inter155, inter155)
reg_4 --> inter156
inter157 --> ILV_2 (inter154, inter156)
reg_8 --> inter157
inter158 --> ILV_2 (inter151, inter157)
reg_16 --> inter158
inter159 --> EXTR_2,1 (inter144)
reg_2 --> inter159
inter160 --> EXTR_2,0 (inter159)
reg_1 --> inter160
inter161 --> EXTR_2,0 (inter160)
reg_2 --> inter161
inter162 --> ILV_2 (inter161, inter161)
reg_4 --> inter162
inter163 --> EXTR_2,1 (inter160)
reg_2 --> inter163
inter164 --> ILV_2 (inter163, inter163)
reg_4 --> inter164
inter165 --> ILV_2 (inter162, inter164)
reg_8 --> inter165
inter166 --> EXTR_2,1 (inter159)
reg_1 --> inter166
inter167 --> EXTR_2,0 (inter166)
reg_2 --> inter167
inter168 --> ILV_2 (inter167, inter167)
reg_4 --> inter168
inter169 --> EXTR_2,1 (inter166)
reg_2 --> inter169
inter170 --> ILV_2 (inter169, inter169)
reg_4 --> inter170
inter171 --> ILV_2 (inter168, inter170)
reg_8 --> inter171
inter172 --> ILV_2 (inter165, inter171)
reg_16 --> inter172
inter173 --> ILV_2 (inter158, inter172)
reg_16 --> inter173
ph174 --> REG
reg_16 --> ph174
inter175 --> EXTR_2,0 (ph174)
reg_4 --> inter175
inter176 --> EXTR_2,0 (inter175)
reg_2 --> inter176
inter177 --> EXTR_2,0 (inter176)
reg_1 --> inter177
inter178 --> EXTR_2,1 (inter177)
reg_2 --> inter178
inter179 --> EXTR_2,1 (inter176)
reg_1 --> inter179
inter180 --> EXTR_2,1 (inter179)
reg_2 --> inter180
inter181 --> ILV_2 (inter178, inter180)
reg_4 --> inter181
inter182 --> EXTR_2,1 (inter175)
reg_2 --> inter182
inter183 --> EXTR_2,0 (inter182)
reg_1 --> inter183
inter184 --> EXTR_2,1 (inter183)
reg_2 --> inter184
inter185 --> EXTR_2,1 (inter182)
reg_1 --> inter185
inter186 --> EXTR_2,1 (inter185)
reg_2 --> inter186
inter187 --> ILV_2 (inter184, inter186)
reg_4 --> inter187
inter188 --> ILV_2 (inter181, inter187)
reg_8 --> inter188
inter189 --> EXTR_2,1 (ph174)
reg_4 --> inter189
inter190 --> EXTR_2,0 (inter189)
reg_2 --> inter190
inter191 --> EXTR_2,0 (inter190)
reg_1 --> inter191
inter192 --> EXTR_2,1 (inter191)
reg_2 --> inter192
inter193 --> EXTR_2,1 (inter190)
reg_1 --> inter193
inter194 --> EXTR_2,1 (inter193)
reg_2 --> inter194
inter195 --> ILV_2 (inter192, inter194)
reg_4 --> inter195
inter196 --> EXTR_2,1 (inter189)
reg_2 --> inter196
inter197 --> EXTR_2,0 (inter196)
reg_1 --> inter197
inter198 --> EXTR_2,1 (inter197)
reg_2 --> inter198
inter199 --> EXTR_2,1 (inter196)
reg_1 --> inter199
inter200 --> EXTR_2,1 (inter199)
reg_2 --> inter200
inter201 --> ILV_2 (inter198, inter200)
reg_4 --> inter201
inter202 --> ILV_2 (inter195, inter201)
reg_8 --> inter202
inter203 --> ILV_2 (inter188, inter202)
reg_16 --> inter203
inter204 --> ILV_2 (inter203, inter203)
reg_16 --> inter204
ph205 --> REG
reg_16 --> ph205
inter206 --> EXTR_2,0 (ph205)
reg_4 --> inter206
inter207 --> EXTR_2,0 (inter206)
reg_2 --> inter207
inter208 --> EXTR_2,0 (inter207)
reg_1 --> inter208
inter209 --> EXTR_2,0 (inter208)
reg_2 --> inter209
inter210 --> EXTR_2,1 (inter207)
reg_1 --> inter210
inter211 --> EXTR_2,0 (inter210)
reg_2 --> inter211
inter212 --> ILV_2 (inter209, inter211)
reg_4 --> inter212
inter213 --> EXTR_2,1 (inter206)
reg_2 --> inter213
inter214 --> EXTR_2,0 (inter213)
reg_1 --> inter214
inter215 --> EXTR_2,0 (inter214)
reg_2 --> inter215
inter216 --> EXTR_2,1 (inter213)
reg_1 --> inter216
inter217 --> EXTR_2,0 (inter216)
reg_2 --> inter217
inter218 --> ILV_2 (inter215, inter217)
reg_4 --> inter218
inter219 --> ILV_2 (inter212, inter218)
reg_8 --> inter219
inter220 --> EXTR_2,1 (ph205)
reg_4 --> inter220
inter221 --> EXTR_2,0 (inter220)
reg_2 --> inter221
inter222 --> EXTR_2,0 (inter221)
reg_1 --> inter222
inter223 --> EXTR_2,0 (inter222)
reg_2 --> inter223
inter224 --> EXTR_2,1 (inter221)
reg_1 --> inter224
inter225 --> EXTR_2,0 (inter224)
reg_2 --> inter225
inter226 --> ILV_2 (inter223, inter225)
reg_4 --> inter226
inter227 --> EXTR_2,1 (inter220)
reg_2 --> inter227
inter228 --> EXTR_2,0 (inter227)
reg_1 --> inter228
inter229 --> EXTR_2,0 (inter228)
reg_2 --> inter229
inter230 --> EXTR_2,1 (inter227)
reg_1 --> inter230
inter231 --> EXTR_2,0 (inter230)
reg_2 --> inter231
inter232 --> ILV_2 (inter229, inter231)
reg_4 --> inter232
inter233 --> ILV_2 (inter226, inter232)
reg_8 --> inter233
inter234 --> ILV_2 (inter219, inter233)
reg_16 --> inter234
inter235 --> ILV_2 (inter234, inter234)
reg_16 --> inter235
*/
