On 09/11/16 10:12, Andre Vieira (lists) wrote:
Hi,
This patch implements support for the ARM ACLE Coprocessor MCR and MRC
intrinsics. See below a table mapping the intrinsics to their respective
instructions:
+-------------------------------------------------------------------+---------------------------------------+
| Intrinsic signature |
Instruction pattern |
+-------------------------------------------------------------------+---------------------------------------+
|void __arm_mcr(coproc, opc1, uint32_t value, CRn, CRm, opc2) |
MCR coproc, opc1, Rt, CRn, CRm, opc2 |
+-------------------------------------------------------------------+---------------------------------------+
|void __arm_mcr2(coproc, opc1, uint32_t value, CRn, CRm, opc2) |
MCR2 coproc, opc1, Rt, CRn, CRm, opc2 |
+-------------------------------------------------------------------+---------------------------------------+
|uint32_t __arm_mrc(coproc, opc1, CRn, CRm, opc2) |
MRC coproc, opc1, Rt, CRn, CRm, opc2 |
+-------------------------------------------------------------------+---------------------------------------+
|uint32_t __arm_mrc2(coproc, opc1, CRn, CRm, opc2) |
MRC2 coproc, opc1, Rt, CRn, CRm, opc2 |
+-------------------------------------------------------------------+---------------------------------------+
Note that any untyped variable in the intrinsic signature is required to
be a compiler-time constant and has the type 'unsigned int'. We do some
boundary checks for coproc:[0-15], opc1[0-7] CR*:[0-31],opc2:[0-7]. If
either of these requirements are not met a diagnostic is issued.
Is this OK for trunk?
Regards,
Andre
gcc/ChangeLog:
2016-11-09 Andre Vieira <andre.simoesdiasvie...@arm.com>
* config/arm/arm.md (<mcr>): New.
(<mrc>): New.
* config/arm/arm.c (arm_coproc_builtin_available): Add
support for mcr, mrc, mcr2 and mrc2.
* config/arm/arm-builtins.c (MCR_QUALIFIERS): Define to...
(arm_mcr_qualifiers): ... this. New.
(MRC_QUALIFIERS): Define to ...
(arm_mrc_qualifiers): ... this. New.
(MCR_QUALIFIERS): Define to ...
(arm_mcr_qualifiers): ... this. New.
* config/arm/arm_acle.h (__arm_mcr, __arm_mrc, __arm_mcr2,
__arm_mrc2): New.
* config/arm/arm_acle_builtins.def (mcr, mcr2, mrc, mrc2): New.
* config/arm/iterators.md (MCRI, mcr, MCR, MRCI, mrc, MRC): New.
* config/arm/unspecs.md (VUNSPEC_MCR, VUNSPEC_MCR2, VUNSPEC_MRC,
VUNSPEC_MRC2): New.
gcc/ChangeLog:
2016-11-09 Andre Vieira <andre.simoesdiasvie...@arm.com>
* gcc.target/arm/acle/mcr.c: New.
* gcc.target/arm/acle/mrc.c: New.
* gcc.target/arm/acle/mcr2.c: New.
* gcc.target/arm/acle/mrc2.c: New.
+(define_insn "<mcr>"
+ [(unspec_volatile [(match_operand:SI 0 "immediate_operand")
+ (match_operand:SI 1 "immediate_operand")
+ (match_operand:SI 2 "s_register_operand")
+ (match_operand:SI 3 "immediate_operand")
+ (match_operand:SI 4 "immediate_operand")
+ (match_operand:SI 5 "immediate_operand")] MCRI)
+ (use (match_dup 2))]
+ "arm_coproc_builtin_available (VUNSPEC_<MCR>)"
+{
+ arm_const_bounds (operands[0], 0, 16);
+ arm_const_bounds (operands[1], 0, 8);
+ arm_const_bounds (operands[3], 0, (1 << 5));
+ arm_const_bounds (operands[4], 0, (1 << 5));
+ arm_const_bounds (operands[5], 0, 8);
+ return "<mcr>\\tp%c0, %1, %2, CR%c3, CR%c4, %5";
+}
+ [(set_attr "length" "4")
+ (set_attr "type" "coproc")])
+
+(define_insn "<mrc>"
+ [(set (match_operand:SI 0 "s_register_operand")
+ (unspec_volatile [(match_operand:SI 1 "immediate_operand")
+ (match_operand:SI 2 "immediate_operand")
+ (match_operand:SI 3 "immediate_operand")
+ (match_operand:SI 4 "immediate_operand")
+ (match_operand:SI 5 "immediate_operand")] MRCI))]
+ "arm_coproc_builtin_available (VUNSPEC_<MRC>)"
+{
+ arm_const_bounds (operands[1], 0, 16);
+ arm_const_bounds (operands[2], 0, 8);
+ arm_const_bounds (operands[3], 0, (1 << 5));
+ arm_const_bounds (operands[4], 0, (1 << 5));
+ arm_const_bounds (operands[5], 0, 8);
+ return "<mrc>\\tp%c1, %2, %0, CR%c3, CR%c4, %5";
+}
+ [(set_attr "length" "4")
+ (set_attr "type" "coproc")])
Same as the previous patch, these operands need constraints.
The MRC ones in particular need a '=' in their constraint string.