This patch fixes an issue in aarch64_classify_address. TImode and TFmode
can either use a 64-bit LDP/STP or 128-bit LDR/STR. The addressing mode
must be carefully modelled as the intersection of both. This is done for
the immediate offsets, however load_store_pair_p must be set as well to
avoid LDP with a PC-relative address if aarch64_pcrelative_literal_loads
is true.
Bootstrap passes with aarch64_pcrelative_literal_loads=true.
ChangeLog:
2015-12-08 Wilco Dijkstra <wdijk...@arm.com>
PR target/78733
* config/aarch64/aarch64.c (aarch64_classify_address):
Set load_store_pair_p for TImode and TFmode.
/testsuite
* gcc.target/aarch64/pr78733.c: New test.
--
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index
48efa37b89551264e25effab1dddbcb490fad085..a95f9c183fcd1db95a8366d1d5b5aa878ee51a6c
100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -4230,8 +4230,11 @@ aarch64_classify_address (struct aarch64_address_info
*info,
enum rtx_code code = GET_CODE (x);
rtx op0, op1;
- /* On BE, we use load/store pair for all large int mode load/stores. */
+ /* On BE, we use load/store pair for all large int mode load/stores.
+ TI/TFmode may also use a load/store pair. */
bool load_store_pair_p = (outer_code == PARALLEL
+ || mode == TImode
+ || mode == TFmode
|| (BYTES_BIG_ENDIAN
&& aarch64_vect_struct_mode_p (mode)));
diff --git a/gcc/testsuite/gcc.target/aarch64/pr78733.c
b/gcc/testsuite/gcc.target/aarch64/pr78733.c
new file mode 100644
index
0000000000000000000000000000000000000000..ce462cedf9f049feb03addfb010b2f339972c337
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr78733.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mpc-relative-literal-loads" } */
+
+__int128
+t (void)
+{
+ return (__int128)1 << 80;
+}
+
+/* { dg-final { scan-assembler "adr" } } */
