> I think you're right. I suppose the new condition should be:
>
> #ifdef LOAD_EXTEND_OP
> /* If this is a typical RISC machine, we only have to worry
> about the way loads are extended. */
> if (!WORD_REGISTER_OPERATIONS
>
> || ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
>
> ? val_signbit_known_set_p (inner_mode, nonzero)
>
> : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND)
> ||
> || !MEM_P (SUBREG_REG (x))))
>
> #endif
Agreed.
> Would you prefer me to make this change or just revert the patch?
Go ahead and make the change, but please do a bit of comment massaging in the
process, for example:
#ifdef LOAD_EXTEND_OP
/* On many CISC machines, accessing an object in a wider mode
causes the high-order bits to become undefined. So they are
not known to be zero. */
if (!WORD_REGISTER_OPERATIONS
/* If this is a typical RISC machine, we only have to worry
about the way loads are extended. */
|| ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
? val_signbit_known_set_p (inner_mode, nonzero)
: LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND)
|| !MEM_P (SUBREG_REG (x))))
#endif
{
if (GET_MODE_PRECISION (GET_MODE (x))
> GET_MODE_PRECISION (inner_mode))
nonzero |= (GET_MODE_MASK (GET_MODE (x))
& ~GET_MODE_MASK (inner_mode));
}
--
Eric Botcazou
