On Thu, Sep 01, 2011 at 04:29:25PM +0100, Andrew Stubbs wrote:
> On 01/09/11 16:26, Andrew Stubbs wrote:
> >OK, fair enough, redundant or not, here's a patch with belt and braces.
> >
> >OK now?
>
> And again, with the patch ....
>
> Andrew
> 2011-09-01 Andrew Stubbs <a...@codesourcery.com>
>
> gcc/
> * config/arm/predicates.md (shift_amount_operand): Ensure shift
> amount is in the range 1..mode_size-1.
>
> gcc/testsuite/
> * gcc.dg/pr50193-1.c: New file.
>
> --- a/gcc/config/arm/predicates.md
> +++ b/gcc/config/arm/predicates.md
> @@ -132,7 +132,9 @@
> (define_predicate "shift_amount_operand"
> (ior (and (match_test "TARGET_ARM")
> (match_operand 0 "s_register_operand"))
> - (match_operand 0 "const_int_operand")))
> + (and (match_operand 0 "const_int_operand")
> + (match_test "INTVAL (op) > 0
> + && INTVAL (op) <= GET_MODE_PRECISION (mode)"))))
IN_RANGE (INTVAL (op), 0, GET_MODE_PRECISION (mode) - 1) ?
1) shift by 0 is well defined (though not sure if arm backend
supports it)
2) shift by mode precision is undefined
3) isn't mode here the mode of the shift operand rather than of the shift
itself (perhaps on arm in all patterns they are the same -
a brief look at arm.amd suggest they are and they are SImode in all
cases, so perhaps just IN_RANGE (INTVAL (op), 0, 31) ?)
Jakub
