On Thu, Aug 11, 2016 at 07:15:17PM -0400, Michael Meissner wrote: > This patch was originally part of patch #3, but I separated it out as I rework > what used to be part of patch #3 to fix some issues. > > This patch adds support for using the ISA 3.0 MTVSRDD instruction when > initializing vector long vectors with variables. I also changed the CPU type > of the other use of MTVSRDD to be vecperm as Pat suggested. > > I added two general tests (vec-init-1.c and vec-init-2.c) that test various > forms of vector initialization to make sure the compiler generates the correct > code. These tests will test optimizations that the future patches will > enhance. I also added a third test (vec-init-3.c) to specifically test > whether > MTVSRDD is generated. > > I did a bootstrap and make check on a little endian power8 system, and there > were no regressions. Can I install this patch to the trunk?
Yes, please do. Thanks, Segher > 2016-08-11 Michael Meissner <meiss...@linux.vnet.ibm.com> > > * config/rs6000/vsx.md (vsx_concat_<mode>): Add support for the > ISA 3.0 MTVSRDD instruction. > (vsx_splat_<mode>): Change cpu type of MTVSRDD instruction to > vecperm. > > [gcc/testsuite] > 2016-08-11 Michael Meissner <meiss...@linux.vnet.ibm.com> > > * gcc.target/powerpc/vec-init-1.c: New tests to test various > vector initialization options. > * gcc.target/powerpc/vec-init-2.c: Likewise. > * gcc.target/powerpc/vec-init-3.c: New test to make sure MTVSRDD > is generated on ISA 3.0.
