On Tue, May 24, 2016 at 8:15 PM, Uros Bizjak <ubiz...@gmail.com> wrote:
> On Tue, May 24, 2016 at 7:18 PM, H.J. Lu <hjl.to...@gmail.com> wrote:
>
>>> Oh, target_flags is only a 32bit integer :(. Is there a reason it
>>> can't be extended to HOST_WIDE_INT, as is the case with
>>> ix86_isa_flags?
>>
>> target_flags is generic, not target specific. I want to limit my
>> change to x86 backend and -mgeneral-regs-only doesn't need
>> to use target_flags .
>
> I have thrown together a quick patch that defines target_flags as
> HOST_WIDE_INT.
>
> (Patch still needs a small correction, so opth-gen.awk will emit
> HOST_WIDE_INT_1 for MASK_* defines, have to go now, but I was able to
> compile functional x86_64-apple-darwin15.5.0 crosscompiler.)
And here is attached complete (but untested!!) patch that should "just
work"(TM).
Uros.
Index: common/config/i386/i386-common.c
===================================================================
--- common/config/i386/i386-common.c (revision 236644)
+++ common/config/i386/i386-common.c (working copy)
@@ -223,6 +223,11 @@
#define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
#define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
+#define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
+ (OPTION_MASK_ISA_MMX_UNSET \
+ | OPTION_MASK_ISA_SSE_UNSET \
+ | OPTION_MASK_ISA_MPX)
+
/* Implement TARGET_HANDLE_OPTION. */
bool
@@ -236,6 +241,21 @@
switch (code)
{
+ case OPT_mgeneral_regs_only:
+ if (value)
+ {
+ /* Disable MPX, MMX, SSE and x87 instructions if only the
+ general registers are allowed.. */
+ opts->x_ix86_isa_flags
+ &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
+ opts->x_ix86_isa_flags_explicit
+ |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
+ opts->x_target_flags &= ~MASK_80387;
+ }
+ else
+ gcc_unreachable ();
+ return true;
+
case OPT_mmmx:
if (value)
{
Index: common.opt
===================================================================
--- common.opt (revision 236644)
+++ common.opt (working copy)
@@ -23,7 +23,7 @@
; Please try to keep this file in ASCII collating order.
Variable
-int target_flags
+HOST_WIDE_INT target_flags
Variable
int optimize
Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c (revision 236645)
+++ config/i386/i386.c (working copy)
@@ -5337,7 +5337,10 @@
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PKU))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU;
- if (!(opts_set->x_target_flags & MASK_80387))
+ /* Don't enable x87 instructions if only the general registers
+ are allowed. */
+ if (!(opts_set->x_target_flags & MASK_GENERAL_REGS_ONLY)
+ && !(opts_set->x_target_flags & MASK_80387))
{
if (processor_alias_table[i].flags & PTA_NO_80387)
opts->x_target_flags &= ~MASK_80387;
Index: config/i386/i386.opt
===================================================================
--- config/i386/i386.opt (revision 236644)
+++ config/i386/i386.opt (working copy)
@@ -74,7 +74,7 @@
;; which flags were passed by the user
Variable
-int ix86_target_flags_explicit
+HOST_WIDE_INT ix86_target_flags_explicit
;; which flags were passed by the user
TargetSave
@@ -897,3 +897,7 @@
mmitigate-rop
Target Var(flag_mitigate_rop) Init(0)
Attempt to avoid generating instruction sequences containing ret bytes.
+
+mgeneral-regs-only
+Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Save
+Generate code which uses only the general registers.
Index: doc/invoke.texi
===================================================================
--- doc/invoke.texi (revision 236644)
+++ doc/invoke.texi (working copy)
@@ -1173,7 +1173,7 @@
-msse2avx -mfentry -mrecord-mcount -mnop-mcount -m8bit-idiv @gol
-mavx256-split-unaligned-load -mavx256-split-unaligned-store @gol
-malign-data=@var{type} -mstack-protector-guard=@var{guard} @gol
--mmitigate-rop}
+-mmitigate-rop -mgeneral-regs-only}
@emph{x86 Windows Options}
@gccoptlist{-mconsole -mcygwin -mno-cygwin -mdll @gol
@@ -24298,6 +24298,12 @@
this option is limited in what it can do and should not be relied
on to provide serious protection.
+@item -mgeneral-regs-only
+@opindex mgeneral-regs-only
+Generate code that uses only the general-purpose registers. This
+prevents the compiler from using floating-point, vector, mask and bound
+registers.
+
@end table
These @samp{-m} switches are supported in addition to the above
Index: doc/tm.texi
===================================================================
--- doc/tm.texi (revision 236644)
+++ doc/tm.texi (working copy)
@@ -652,7 +652,7 @@
it yourself.
@end defmac
-@deftypevar {extern int} target_flags
+@deftypevar {extern HOST_WIDE_INT} target_flags
This variable is declared in @file{options.h}, which is included before
any target-specific headers.
@end deftypevar
Index: doc/tm.texi.in
===================================================================
--- doc/tm.texi.in (revision 236644)
+++ doc/tm.texi.in (working copy)
@@ -650,7 +650,7 @@
it yourself.
@end defmac
-@deftypevar {extern int} target_flags
+@deftypevar {extern HOST_WIDE_INT} target_flags
This variable is declared in @file{options.h}, which is included before
any target-specific headers.
@end deftypevar
Index: gensupport.c
===================================================================
--- gensupport.c (revision 236644)
+++ gensupport.c (working copy)
@@ -36,7 +36,7 @@
/* In case some macros used by files we include need it, define this here. */
-int target_flags;
+HOST_WIDE_INT target_flags;
int insn_elision = 1;
Index: opth-gen.awk
===================================================================
--- opth-gen.awk (revision 236644)
+++ opth-gen.awk (working copy)
@@ -349,34 +349,36 @@
if (name != "" && mask_bits[name] == 0) {
mask_bits[name] = 1
vname = var_name(flags[i])
- mask = "MASK_"
- mask_1 = "1"
- if (vname != "") {
+ if (vname == "") {
+ mask = "MASK_"
+ extra_mask_bits[name] = 1
+ } else
mask = "OPTION_MASK_"
- if (host_wide_int[vname] == "yes")
- mask_1 = "HOST_WIDE_INT_1"
- } else
- extra_mask_bits[name] = 1
+ if (vname == "" || host_wide_int[vname] == "yes")
+ mask_1 = "HOST_WIDE_INT_1"
+ else
+ mask_1 = "1"
+
print "#define " mask name " (" mask_1 " << " masknum[vname]++
")"
}
}
for (i = 0; i < n_extra_masks; i++) {
if (extra_mask_bits[extra_masks[i]] == 0)
- print "#define MASK_" extra_masks[i] " (1 << " masknum[""]++ ")"
+ print "#define MASK_" extra_masks[i] " (HOST_WIDE_INT_1 << "
masknum[""]++ ")"
}
for (var in masknum) {
- if (var != "" && host_wide_int[var] == "yes") {
+ if (var == "" || host_wide_int[var] == "yes") {
print" #if defined(HOST_BITS_PER_WIDE_INT) && " masknum[var] "
>= HOST_BITS_PER_WIDE_INT"
- print "#error too many masks for " var
- print "#endif"
- }
- else if (masknum[var] > 31) {
if (var == "")
print "#error too many target masks"
else
print "#error too many masks for " var
+ print "#endif"
}
+ else if (masknum[var] > 31) {
+ print "#error too many masks for " var
+ }
}
print ""
