These intrinsics were implemented before the instruction pattern
"aarch64_rsqrte<mode>" added, that these intrinsics were implemented through
inline assembly.
This mirgrate the implementation to builtin.
gcc/
2016-05-23 Jiong Wang <jiong.w...@arm.com>
* config/aarch64/aarch64-builtins.def (rsqrte): New builtins
for modes
VALLF.
* config/aarch64/aarch64-simd.md (aarch64_rsqrte_<mode>2):
Rename to
"aarch64_rsqrte<mode>".
* config/aarch64/aarch64.c (get_rsqrte_type): Update gen* name.
* config/aarch64/arm_neon.h (vrsqrts_f32): Remove inline
assembly. Use
builtin.
(vrsqrted_f64): Likewise.
(vrsqrte_f32): Likewise.
(vrsqrteq_f32): Likewise.
(vrsqrteq_f64): Likewise.
>From 4921317940fe69353cd057cc329943350bc45adf Mon Sep 17 00:00:00 2001
From: "Jiong.Wang" <jiong.w...@arm.com>
Date: Mon, 23 May 2016 12:12:19 +0100
Subject: [PATCH 3/6] 3
---
gcc/config/aarch64/aarch64-builtins.def | 3 ++
gcc/config/aarch64/aarch64-simd.md | 2 +-
gcc/config/aarch64/aarch64.c | 10 ++--
gcc/config/aarch64/arm_neon.h | 87 ++++++++++++---------------------
4 files changed, 41 insertions(+), 61 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-builtins.def b/gcc/config/aarch64/aarch64-builtins.def
index 5e6280c..32bcd06 100644
--- a/gcc/config/aarch64/aarch64-builtins.def
+++ b/gcc/config/aarch64/aarch64-builtins.def
@@ -459,3 +459,6 @@
BUILTIN_VALLI (BINOP_SUS, ucvtf, 3)
BUILTIN_VALLF (BINOP, fcvtzs, 3)
BUILTIN_VALLF (BINOP_USS, fcvtzu, 3)
+
+ /* Implemented by aarch64_rsqrte<mode>. */
+ BUILTIN_VALLF (UNOP, rsqrte, 0)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 66ca2de..c34d21e 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -382,7 +382,7 @@
[(set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")]
)
-(define_insn "aarch64_rsqrte_<mode>2"
+(define_insn "aarch64_rsqrte<mode>"
[(set (match_operand:VALLF 0 "register_operand" "=w")
(unspec:VALLF [(match_operand:VALLF 1 "register_operand" "w")]
UNSPEC_RSQRTE))]
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index bd45a7d..18a8c1e 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -7358,11 +7358,11 @@ get_rsqrte_type (machine_mode mode)
{
switch (mode)
{
- case DFmode: return gen_aarch64_rsqrte_df2;
- case SFmode: return gen_aarch64_rsqrte_sf2;
- case V2DFmode: return gen_aarch64_rsqrte_v2df2;
- case V2SFmode: return gen_aarch64_rsqrte_v2sf2;
- case V4SFmode: return gen_aarch64_rsqrte_v4sf2;
+ case DFmode: return gen_aarch64_rsqrtedf;
+ case SFmode: return gen_aarch64_rsqrtesf;
+ case V2DFmode: return gen_aarch64_rsqrtev2df;
+ case V2SFmode: return gen_aarch64_rsqrtev2sf;
+ case V4SFmode: return gen_aarch64_rsqrtev4sf;
default: gcc_unreachable ();
}
}
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index bd712fc..4c9976e 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -9163,17 +9163,6 @@ vqrdmulhq_n_s32 (int32x4_t a, int32_t b)
result; \
})
-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-vrsqrte_f32 (float32x2_t a)
-{
- float32x2_t result;
- __asm__ ("frsqrte %0.2s,%1.2s"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
vrsqrte_f64 (float64x1_t a)
{
@@ -9196,39 +9185,6 @@ vrsqrte_u32 (uint32x2_t a)
return result;
}
-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
-vrsqrted_f64 (float64_t a)
-{
- float64_t result;
- __asm__ ("frsqrte %d0,%d1"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
-vrsqrteq_f32 (float32x4_t a)
-{
- float32x4_t result;
- __asm__ ("frsqrte %0.4s,%1.4s"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
-vrsqrteq_f64 (float64x2_t a)
-{
- float64x2_t result;
- __asm__ ("frsqrte %0.2d,%1.2d"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
vrsqrteq_u32 (uint32x4_t a)
{
@@ -9240,17 +9196,6 @@ vrsqrteq_u32 (uint32x4_t a)
return result;
}
-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
-vrsqrtes_f32 (float32_t a)
-{
- float32_t result;
- __asm__ ("frsqrte %s0,%s1"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
vrsqrts_f32 (float32x2_t a, float32x2_t b)
{
@@ -21504,6 +21449,38 @@ vrshrd_n_u64 (uint64_t __a, const int __b)
return __builtin_aarch64_urshr_ndi_uus (__a, __b);
}
+/* vrsqrte. */
+
+__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+vrsqrtes_f32 (float32_t a)
+{
+ return __builtin_aarch64_rsqrtesf (a);
+}
+
+__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+vrsqrted_f64 (float64_t a)
+{
+ return __builtin_aarch64_rsqrtedf (a);
+}
+
+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+vrsqrte_f32 (float32x2_t a)
+{
+ return __builtin_aarch64_rsqrtev2sf (a);
+}
+
+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+vrsqrteq_f32 (float32x4_t a)
+{
+ return __builtin_aarch64_rsqrtev4sf (a);
+}
+
+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+vrsqrteq_f64 (float64x2_t a)
+{
+ return __builtin_aarch64_rsqrtev2df (a);
+}
+
/* vrsra */
__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
--
1.9.1
