On Sat, Oct 17, 2015 at 4:30 AM, H.J. Lu <hongjiu...@intel.com> wrote:
> -miamcu specifies how parameters are passed to functions and how value
> is returned from a function. Inside function, we can use instructions
> supported by -march=XXX. -miamcu -march=haswell can generate x87, SSE
> and AVX instructions as long as the IA MCU psABI is followed. But since
> Lakemont processor doesn't support x87 instructions, we shouldn't
> generate x87 instructions with -march=lakemont. This patch separates
> code generation from -miamcu and makes -march=lakemont not to generate
> x87 instructions.
>
> Tested on x86-64. OK for trunk?
>
> Thanks.
>
> H.J.
> ----
> gcc/
>
> PR target/67963
> PR target/67985
> * common/config/i386/i386-common.c (ix86_handle_option): Remove
> OPT_miamcu handling.
> * config/i386/i386.c (PTA_NO_80387): New macro.
> (processor_alias_table): Add PTA_NO_80387 to lakemont.
> (ix86_option_override_internal): Update MASK_80387 from
> PTA_NO_80387. Don't warn x87/MMX/SSE/AVX for -miamcu. Warn
> SSE math only if 80387 is supported. Don't change
> MASK_FLOAT_RETURNS.
> (ix86_valid_target_attribute_tree): Enable FPMATH_387 only if
> 80387 is supported.
> * config/i386/i386.h (TARGET_FLOAT_RETURNS_IN_80387): True only
> if TARGET_80387 is true and TARGET_IAMCU is false.
> (TARGET_FLOAT_RETURNS_IN_80387_P): True only if TARGET_80387_P
> is true and TARGET_IAMCU_P is false.
>
> gcc/testsuite/
>
> PR target/67963
> PR target/67985
> * gcc.target/i386/pr67963-1.c: New test.
> * gcc.target/i386/pr67963-2.c: Likewise.
> * gcc.target/i386/pr67963-3.c: Likewise.
> * gcc.target/i386/pr67985-1.c: Likewise.
> * gcc.target/i386/pr67985-2.c: Likewise.
> * gcc.target/i386/pr67985-3.c: Likewise.
OK.
Thanks,
Uros.
> gcc/common/config/i386/i386-common.c | 16 +-----------
> gcc/config/i386/i386.c | 41
> ++++++++++++++-----------------
> gcc/config/i386/i386.h | 8 ++++--
> gcc/testsuite/gcc.target/i386/pr67963-1.c | 9 +++++++
> gcc/testsuite/gcc.target/i386/pr67963-2.c | 11 +++++++++
> gcc/testsuite/gcc.target/i386/pr67963-3.c | 11 +++++++++
> gcc/testsuite/gcc.target/i386/pr67985-1.c | 11 +++++++++
> gcc/testsuite/gcc.target/i386/pr67985-2.c | 13 ++++++++++
> gcc/testsuite/gcc.target/i386/pr67985-3.c | 12 +++++++++
> 9 files changed, 93 insertions(+), 39 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr67963-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/pr67963-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/pr67963-3.c
> create mode 100644 gcc/testsuite/gcc.target/i386/pr67985-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/pr67985-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/pr67985-3.c
>
> diff --git a/gcc/common/config/i386/i386-common.c
> b/gcc/common/config/i386/i386-common.c
> index 79b2472..0f8c3e1 100644
> --- a/gcc/common/config/i386/i386-common.c
> +++ b/gcc/common/config/i386/i386-common.c
> @@ -223,7 +223,7 @@ along with GCC; see the file COPYING3. If not see
>
> bool
> ix86_handle_option (struct gcc_options *opts,
> - struct gcc_options *opts_set,
> + struct gcc_options *opts_set ATTRIBUTE_UNUSED,
> const struct cl_decoded_option *decoded,
> location_t loc)
> {
> @@ -232,20 +232,6 @@ ix86_handle_option (struct gcc_options *opts,
>
> switch (code)
> {
> - case OPT_miamcu:
> - if (value)
> - {
> - /* Turn off x87/MMX/SSE/AVX codegen for -miamcu. */
> - opts->x_target_flags &= ~MASK_80387;
> - opts_set->x_target_flags |= MASK_80387;
> - opts->x_ix86_isa_flags &= ~(OPTION_MASK_ISA_MMX_UNSET
> - | OPTION_MASK_ISA_SSE_UNSET);
> - opts->x_ix86_isa_flags_explicit |= (OPTION_MASK_ISA_MMX_UNSET
> - | OPTION_MASK_ISA_SSE_UNSET);
> -
> - }
> - return true;
> -
> case OPT_mmmx:
> if (value)
> {
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index 33e0cff..270199c 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -4295,6 +4295,7 @@ ix86_option_override_internal (bool main_args_p,
> #define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56)
> #define PTA_MWAITX (HOST_WIDE_INT_1 << 57)
> #define PTA_CLZERO (HOST_WIDE_INT_1 << 58)
> +#define PTA_NO_80387 (HOST_WIDE_INT_1 << 59)
>
> #define PTA_CORE2 \
> (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
> @@ -4339,7 +4340,7 @@ ix86_option_override_internal (bool main_args_p,
> {"i486", PROCESSOR_I486, CPU_NONE, 0},
> {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
> {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
> - {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, 0},
> + {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
> {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
> {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
> {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW |
> PTA_PRFCHW},
> @@ -4920,6 +4921,13 @@ ix86_option_override_internal (bool main_args_p,
> && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MWAITX))
> opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MWAITX;
>
> + if (!(opts_set->x_target_flags & MASK_80387))
> + {
> + if (processor_alias_table[i].flags & PTA_NO_80387)
> + opts->x_target_flags &= ~MASK_80387;
> + else
> + opts->x_target_flags |= MASK_80387;
> + }
> break;
> }
>
> @@ -4929,20 +4937,6 @@ ix86_option_override_internal (bool main_args_p,
> if (TARGET_X32 && (ix86_isa_flags & OPTION_MASK_ISA_MPX))
> error ("Intel MPX does not support x32");
>
> - if (TARGET_IAMCU_P (opts->x_target_flags))
> - {
> - /* Verify that x87/MMX/SSE/AVX is off for -miamcu. */
> - if (TARGET_80387_P (opts->x_target_flags))
> - sorry ("X87 FPU isn%'t supported in Intel MCU psABI");
> - else if ((opts->x_ix86_isa_flags & (OPTION_MASK_ISA_MMX
> - | OPTION_MASK_ISA_SSE
> - | OPTION_MASK_ISA_AVX)))
> - sorry ("%s isn%'t supported in Intel MCU psABI",
> - TARGET_MMX_P (opts->x_ix86_isa_flags)
> - ? "MMX"
> - : TARGET_SSE_P (opts->x_ix86_isa_flags) ? "SSE" : "AVX");
> - }
> -
> if (!strcmp (opts->x_ix86_arch_string, "generic"))
> error ("generic CPU can be used only for %stune=%s %s",
> prefix, suffix, sw);
> @@ -5226,8 +5220,11 @@ ix86_option_override_internal (bool main_args_p,
> {
> if (!TARGET_SSE_P (opts->x_ix86_isa_flags))
> {
> - warning (0, "SSE instruction set disabled, using 387
> arithmetics");
> - opts->x_ix86_fpmath = FPMATH_387;
> + if (TARGET_80387_P (opts->x_target_flags))
> + {
> + warning (0, "SSE instruction set disabled, using 387
> arithmetics");
> + opts->x_ix86_fpmath = FPMATH_387;
> + }
> }
> else if ((opts->x_ix86_fpmath & FPMATH_387)
> && !TARGET_80387_P (opts->x_target_flags))
> @@ -5253,10 +5250,6 @@ ix86_option_override_internal (bool main_args_p,
> else
> opts->x_ix86_fpmath = TARGET_FPMATH_DEFAULT_P (opts->x_ix86_isa_flags);
>
> - /* If the i387 is disabled, then do not return values in it. */
> - if (!TARGET_80387_P (opts->x_target_flags))
> - opts->x_target_flags &= ~MASK_FLOAT_RETURNS;
> -
> /* Use external vectorized library in vectorizing intrinsics. */
> if (opts_set->x_ix86_veclibabi_type)
> switch (opts->x_ix86_veclibabi_type)
> @@ -6155,7 +6148,11 @@ ix86_valid_target_attribute_tree (tree args,
> else if (!TARGET_64BIT_P (opts->x_ix86_isa_flags)
> && TARGET_SSE_P (opts->x_ix86_isa_flags))
> {
> - opts->x_ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
> + if (TARGET_80387_P (opts->x_target_flags))
> + opts->x_ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE
> + | FPMATH_387);
> + else
> + opts->x_ix86_fpmath = (enum fpmath_unit) FPMATH_SSE;
> opts_set->x_ix86_fpmath = (enum fpmath_unit) 1;
> }
>
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index 435312f..be96c75 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -295,8 +295,12 @@ extern const struct processor_costs ix86_size_cost;
> (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387)
> #endif
>
> -#define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
> -#define TARGET_FLOAT_RETURNS_IN_80387_P(x) TARGET_FLOAT_RETURNS_P(x)
> +/* If the i387 is disabled or -miamcu is used , then do not return
> + values in it. */
> +#define TARGET_FLOAT_RETURNS_IN_80387 \
> + (TARGET_FLOAT_RETURNS && TARGET_80387 && !TARGET_IAMCU)
> +#define TARGET_FLOAT_RETURNS_IN_80387_P(x) \
> + (TARGET_FLOAT_RETURNS_P(x) && TARGET_80387_P(x) && !TARGET_IAMCU_P(x))
>
> /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
> compile-time constant. */
> diff --git a/gcc/testsuite/gcc.target/i386/pr67963-1.c
> b/gcc/testsuite/gcc.target/i386/pr67963-1.c
> new file mode 100644
> index 0000000..1b6e596
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr67963-1.c
> @@ -0,0 +1,9 @@
> +/* { dg-do compile { target ia32 } } */
> +/* { dg-options "-O2 -march=lakemont" } */
> +
> +float foo (void)
> +{
> + return 0.0f;
> +}
> +
> +/* { dg-final { scan-assembler-not "fldz" } } */
> diff --git a/gcc/testsuite/gcc.target/i386/pr67963-2.c
> b/gcc/testsuite/gcc.target/i386/pr67963-2.c
> new file mode 100644
> index 0000000..76c929d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr67963-2.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile { target ia32 } } */
> +/* { dg-options "-O2 -march=pentium" } */
> +
> +float
> +__attribute__((target("arch=lakemont")))
> +foo (void)
> +{
> + return 0.0f;
> +}
> +
> +/* { dg-final { scan-assembler-not "fldz" } } */
> diff --git a/gcc/testsuite/gcc.target/i386/pr67963-3.c
> b/gcc/testsuite/gcc.target/i386/pr67963-3.c
> new file mode 100644
> index 0000000..b8e1900
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr67963-3.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile { target ia32 } } */
> +/* { dg-options "-O2 -march=lakemont" } */
> +
> +float
> +__attribute__((target("arch=pentium")))
> +foo (void)
> +{
> + return 0.0f;
> +}
> +
> +/* { dg-final { scan-assembler "fldz" } } */
> diff --git a/gcc/testsuite/gcc.target/i386/pr67985-1.c
> b/gcc/testsuite/gcc.target/i386/pr67985-1.c
> new file mode 100644
> index 0000000..28d0f86
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr67985-1.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile { target ia32 } } */
> +/* { dg-options "-O2 -miamcu -msse2 -mfpmath=sse -mtune=generic" } */
> +
> +float
> +foo (float x, float y)
> +{
> + return x * y;
> +}
> +
> +/* { dg-final { scan-assembler "mulss" } } */
> +/* { dg-final { scan-assembler "movd\[ \t\]%xmm\[0-7\], %eax" } } */
> diff --git a/gcc/testsuite/gcc.target/i386/pr67985-2.c
> b/gcc/testsuite/gcc.target/i386/pr67985-2.c
> new file mode 100644
> index 0000000..9c7a25a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr67985-2.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile { target ia32 } } */
> +/* { dg-options "-O2 -miamcu -msse2 -mfpmath=sse -mtune=generic" } */
> +
> +float
> +__attribute__((target("arch=lakemont")))
> +foo (float x, float y)
> +{
> + return x * y;
> +}
> +
> +/* { dg-final { scan-assembler-not "mulss" } } */
> +/* { dg-final { scan-assembler-not "movl\[ \t\].*, %eax" } } */
> +/* { dg-final { scan-assembler "call\[ \t\]__mulsf3" } } */
> diff --git a/gcc/testsuite/gcc.target/i386/pr67985-3.c
> b/gcc/testsuite/gcc.target/i386/pr67985-3.c
> new file mode 100644
> index 0000000..58c379c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr67985-3.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile { target ia32 } } */
> +/* { dg-options "-O2 -miamcu -march=lakemont" } */
> +
> +float
> +__attribute__((target("arch=haswell")))
> +foo (float x, float y)
> +{
> + return x * y;
> +}
> +
> +/* { dg-final { scan-assembler "mulss" } } */
> +/* { dg-final { scan-assembler "movd\[ \t\]%xmm\[0-7\], %eax" } } */
> --
> 2.4.3
>
