On 03/08/15 13:33, Uros Bizjak wrote:
Hello!
2015-07-30 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* ifcvt.c (noce_try_store_flag_constants): Make logic of the case
when diff == STORE_FLAG_VALUE or diff == -STORE_FLAG_VALUE more
explicit. Prefer to add the flag whenever possible.
(noce_process_if_block): Try noce_try_store_flag_constants before
noce_try_cmove.
2015-07-30 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* gcc.target/aarch64/csel_bfx_1.c: New test.
* gcc.target/aarch64/csel_imms_inc_1.c: Likewise.
This patch regressed following tests on x86_64:
FAIL: gcc.target/i386/cmov2.c scan-assembler sbb
FAIL: gcc.target/i386/cmov3.c scan-assembler cmov[^3]
Sorry for that :(
I could have sworn they passed for me during my run...
While cmov3 case is questionable by itself in light of PR56309 [1],
the cnov2 case regressed from:
cmpl %edi, %esi
sbbl %eax, %eax
andl $-10, %eax
addl $5, %eax
ret
to:
xorl %eax, %eax
cmpl %esi, %edi
setbe %al
negl %eax
andl $10, %eax
subl $5, %eax
ret
Please note that sbb (aka {*x86_movsicc_0_m1} ) is not generated
anymore. Non-QImode setcc instructions are problematic on x86, since
they need to be zero-extended to their full length.
The transformation at fault in noce_try_store_flag_constants is:
/* if (test) x = a; else x = b;
=> x = (-(test != 0) & (b - a)) + a; */
I suppose we want to not perform this transformation on x86.
The question is, on what characteristic of the target do we want to gate this
on?
[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56309
Uros.
