[PATCH][AArch64] Add zero_extend variants of logical+not ops

[Kyrill Tkachov]

Hi all,

We were missing the patterns for the zero-extend versions of the negated-logic 
ops, bic,orn,eon
leading to redundant zero-extends being generated for code like:

unsigned long
bar (unsigned int a, unsigned int b)
{
  return a ^ ~b;
}

unsigned long
bar2 (unsigned int a, unsigned int b)
{
  return a & ~b;
}


With this patch for the above we can generate:
bar:
    eon    w0, w1, w0
    ret

bar2:
    bic    w0, w0, w1
    ret


instead of:
bar:
    eon    w0, w1, w0
    uxtw    x0, w0
    ret

bar2:
    bic    w0, w0, w1
    uxtw    x0, w0
    ret


Bootstrapped and tested on aarch64-linux.
Ok for trunk?

Thanks,
Kyrill

2015-04-21  Kyrylo Tkachov  <kyrylo.tkac...@arm.com>

    * config/aarch64/aarch64.md (*<NLOGICAL:optab>_one_cmplsidi3_ze):
    New pattern.
    (*xor_one_cmplsidi3_ze): Likewise.

commit 8ff7aaaa6787ce2674b918e1e6ed8b09cafb6b7a
Author: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
Date:   Mon Mar 2 16:20:10 2015 +0000

    [AArch64] Add zero_extend variants of logical+not ops

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 4aa8f5c..1a7f888 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3058,6 +3058,26 @@ (define_insn "*<NLOGICAL:optab>_one_cmpl<mode>3"
    (set_attr "simd" "*,yes")]
 )
 
+(define_insn "*<NLOGICAL:optab>_one_cmplsidi3_ze"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI
+	  (NLOGICAL:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
+	               (match_operand:SI 2 "register_operand" "r"))))]
+  ""
+  "<NLOGICAL:nlogical>\\t%w0, %w2, %w1"
+  [(set_attr "type" "logic_reg")]
+)
+
+(define_insn "*xor_one_cmplsidi3_ze"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (zero_extend:DI
+          (not:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
+                          (match_operand:SI 2 "register_operand" "r")))))]
+  ""
+  "eon\\t%w0, %w1, %w2"
+  [(set_attr "type" "logic_reg")]
+)
+
 ;; (xor (not a) b) is simplify_rtx-ed down to (not (xor a b)).
 ;; eon does not operate on SIMD registers so the vector variant must be split.
 (define_insn_and_split "*xor_one_cmpl<mode>3"