On Wed, May 25, 2011 at 6:20 PM, H.J. Lu <hjl.to...@gmail.com> wrote:
>>>>> We are working on a new optimization, which turns off TARGET_MOVX. >>>>> GCC generates: >>>>> >>>>> movb %ah, %dil >>>>> >>>>> But %ah can only be used with %[abcd][hl]. This patch adds QIreg_operand >>>>> and uses it in *movqi_extv_1_rex64/*movqi_extzv_2_rex64. OK for trunk >>>>> if there is no regression? and Replace >> q_regs_operand with QIreg_operand. >> ( >>>> >>>> If this is the case, then please change "q_regs_operand" predicate to >>>> accept just QI_REG_P registers. >>>> >>> >>> I thought about it. It is a problem only with %[abcd]h. I am not sure if >>> changing q_regs_operand to accept just QI_REG_P registers will negatively >>> impact >> >> I see. The patch is OK then, but for consistency, please change the >> predicate of *movqi_extv_1*movqi_extzv_2 as well. Oh, and the >> "register_operand" check in "type" calculation can be removed. >> >> Thanks, >> Uros. >> > > This is what I checked in. > > Thanks. > > -- > H.J. > --- > 2011-05-25 H.J. Lu <hongjiu...@intel.com> > > PR target/49142 > * config/i386/i386.md (*movqi_extv_1_rex64): Remove > "register_operand" check and replace q_regs_operand with > QIreg_operand in "type" calculation. > (*movqi_extv_1): Likewise. > (*movqi_extzv_2_rex64): Likewise. > (*movqi_extzv_2): Likewise. Er, I didn't mean to remove register_operand check from 32bit patterns... there, operand 0 can also be memory operand due to "nonimmediate_operand" constraint. Uros.
