https://gcc.gnu.org/g:427f8e7d1150239728bccec76c168bbed39e8061
commit r17-1450-g427f8e7d1150239728bccec76c168bbed39e8061 Author: Georg-Johann Lay <[email protected]> Date: Tue Jun 9 16:41:26 2026 +0200 AVR: Fix some typos in comments. gcc/ * config/avr/avr.md: Fix typos in comments. * config/avr/avr-fixed.md: Same. * config/avr/avr-passes.cc: Same * config/avr/avr-passes-fuse-move.h: Same. Diff: --- gcc/config/avr/avr-fixed.md | 6 +++--- gcc/config/avr/avr-passes-fuse-move.h | 4 ++-- gcc/config/avr/avr-passes.cc | 19 ++++++++++--------- gcc/config/avr/avr.md | 13 ++++++------- 4 files changed, 21 insertions(+), 21 deletions(-) diff --git a/gcc/config/avr/avr-fixed.md b/gcc/config/avr/avr-fixed.md index 7859f89bb5f3..d638d0b68d7b 100644 --- a/gcc/config/avr/avr-fixed.md +++ b/gcc/config/avr/avr-fixed.md @@ -106,7 +106,7 @@ ;; Fixme: It would be nice if we could expand the 32-bit versions to a ;; transparent libgcc call if $2 is a REG. Problem is that it is ;; not possible to describe that addition is commutative. -;; And defining register classes/constraintrs for the involved hard +;; And defining register classes/constraints for the involved hard ;; registers and let IRA do the work, yields inacceptable bloated code. ;; Thus, we have to live with the up to 11 instructions that are output ;; for these 32-bit saturated operations. @@ -164,7 +164,7 @@ ;; Fixme: This will always result in 0. Dunno why simplify-rtx.cc says ;; "unknown" on how to optimize this. libgcc call would be in order, ;; but the performance is *PLAIN* *HORROR* because the optimizers don't -;; manage to optimize out MEMCPY that's sprincled all over fixed-bit.c */ +;; manage to optimize out MEMCPY that's sprinkled all over fixed-bit.c */ (define_expand "usneg<mode>2" [(parallel [(match_operand:ALL124U 0 "register_operand" "") @@ -633,7 +633,7 @@ }) ;; Expand rounding with known rounding points inline so that the addend / mask -;; will be consumed by operation with immediate operands and there is no +;; will be consumed by operation with immediate operands, and there is no ;; need for a shift with variable offset. ;; "roundqq3_const" "rounduqq3_const" diff --git a/gcc/config/avr/avr-passes-fuse-move.h b/gcc/config/avr/avr-passes-fuse-move.h index a46afa54f414..47249c35c142 100644 --- a/gcc/config/avr/avr-passes-fuse-move.h +++ b/gcc/config/avr/avr-passes-fuse-move.h @@ -517,7 +517,7 @@ struct ply_t return memo.value (regno, size); } - // Helper for dump_plys: Value of 1st source arg provided it is a register. + // Helper for dump_plys: Value of 1st source arg provided is a register. int src1_value (const memento_t &memo) const { int rsrc = regno; @@ -718,7 +718,7 @@ struct ply_t }; // ply_t -// A set of ply_t's. We prefer std:array (with some expected upper +// A set of ply_t's. We prefer std::array (with some expected upper // bound for the number of ply_t's as generated by bbinfo_t::get_plies()) // over std::vector. That way, all plies_t are only allocated once as // elements of avr_pass_fuse_move::BInfo. diff --git a/gcc/config/avr/avr-passes.cc b/gcc/config/avr/avr-passes.cc index 5ade9971806f..46ac9ca238a4 100644 --- a/gcc/config/avr/avr-passes.cc +++ b/gcc/config/avr/avr-passes.cc @@ -151,7 +151,7 @@ single_set_with_scratch (rtx_insn *insn, int ®no_scratch) using gprmask_t = uint32_t; // True when this is a valid GPR number for ordinary code, e.g. -// registers wider than 2 bytes have to start at an exven regno. +// registers wider than 2 bytes have to start at an even regno. // TMP_REG and ZERO_REG are not considered valid, even though // the C source can use register vars with them. static inline bool @@ -1251,7 +1251,7 @@ public: // Append PLY to .plies[]. A SET or BLD ply may start a new sequence of // SETs or BLDs and gets assigned the overhead of the sequence like for an -// initial SET or CLT instruction. A SET ply my be added in two flavours: +// initial SET or CLT instruction. A SET ply may be added in two flavours: // One that starts a sequence of single_sets, and one that represents the // payload of a set_some insn. MEMO is the GPR state prior to PLY. void @@ -1579,7 +1579,7 @@ plies_t::emit_sets (const insninfo_t &ii, int &n_insns, const memento_t &memo, // Try to find an operation such that Y = op (X). // Shifts and rotates are regarded as unary operations with -// an implied 2nd operand or 1 or 4, respectively. +// an implied 2nd operand of 1 or 4, respectively. static rtx_code find_arith (uint8_t y, uint8_t x) { @@ -2471,8 +2471,9 @@ bbinfo_t::find_plies (int len, const insninfo_t &ii, const memento_t &memo0) } -// Run .find_plies() and return true when .fpd->solution is a sequence of ply_t's -// that represents II, a REG = CONST insn. MEMO is the GPR state prior to II. +// Run .find_plies() and return true when .fpd->solution is a sequence +// of ply_t's that represents II, a REG = CONST insn. MEMO is the +// GPR state prior to II. bool bbinfo_t::run_find_plies (const insninfo_t &ii, const memento_t &memo) const { @@ -3991,7 +3992,7 @@ avr_is_casesi_sequence (basic_block bb, rtx_insn *insn, rtx_insn *insns[5]) /* We have to deal with quite some operands. Extracting them by hand would be tedious, therefore wrap the insn patterns into a parallel, - run recog against it and then use insn extract to get the operands. */ + run recog against it, and then use insn extract to get the operands. */ rtx_insn *xinsn = avr_parallel_insn_from_insns (insns); @@ -4078,7 +4079,7 @@ avr_optimize_casesi (rtx_insn *insns[5], rtx *xop) // makes no sense to have case values outside the mode range. Notice // that case labels which are unreachable because they are outside the // mode of the switch value (e.g. "case -1" for uint8_t) have already - // been thrown away by the middle-end. + // been thrown away by the middle end. if (SIGN_EXTEND == code && low_idx >= imin @@ -4273,7 +4274,7 @@ public: } // Cloning is required because we are running one instance of the pass - // before peephole2. and a second one after cprop_hardreg. + // before peephole2, and a second one after cprop_hardreg. opt_pass * clone () final override { return make_avr_pass_fuse_add (m_ctxt); @@ -4757,7 +4758,7 @@ avr_pass_fuse_add::fuse_mem_add (Mem_Insn &mem, Add_Insn &add) return next; } -/* Try to post-reload combine PLUS with CONST_INt of pointer registers with: +/* Try to post-reload combine PLUS with CONST_INT of pointer registers with: - Sets to a constant address. - PLUS insn of that kind. - Indirect loads and stores. diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 3b70dc18aab3..6f78290fe38e 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -121,7 +121,6 @@ (const_string "arith")) ;; The size of instructions in bytes. -;; XXX may depend from "cc" (define_attr "length" "" (cond [(eq_attr "type" "branch") @@ -4879,11 +4878,11 @@ ;; Overlapping non-HImode registers often (but not always) need a scratch. ;; The best we can do is use early clobber alternative "#&r" so that -;; completely non-overlapping operands dont get a scratch but # so register +;; completely non-overlapping operands don't get a scratch but # so register ;; allocation does not prefer non-overlapping. -;; Split word aligned rotates using scratch that is mode dependent. +;; Split word aligned rotates using a mode-dependent scratch. ;; "*rotwhi" ;; "*rotwsi" @@ -4905,7 +4904,7 @@ }) -;; Split byte aligned rotates using scratch that is always QI mode. +;; Split byte aligned rotates using a QImode scratch. ;; "*rotbhi" ;; "*rotbpsi" @@ -5051,7 +5050,7 @@ (match_dup 2)))]) ;; ??? Combiner does not recognize that it could split the following insn; -;; presumably because he has no register handy? +;; presumably because it has no register handy? ;; "*ashluqihiqi3.mem" ;; "*ashlsqihiqi3.mem" @@ -9983,8 +9982,8 @@ ;; even on machines that don't have MUL instructions or that ;; have to perform the multiplication by means of a libgcc call. ;; Try to fix that below. Notice that on AVR_TINY no MUL insn is -;; available since is is performed as a libgcc call from which we -;; cannot roll back. With !AVR_HAVR_MULMUL it's a transparent call +;; available since it is performed as a libgcc call from which we +;; cannot roll back. With !AVR_HAVE_MUL it's a transparent call ;; from avr.md so we can get rid of that at least. ;; Map
