https://gcc.gnu.org/g:871bd9f57a5e5f4d987d96b1b80d5b3de2dcace0
commit r17-1449-g871bd9f57a5e5f4d987d96b1b80d5b3de2dcace0 Author: Wilco Dijkstra <[email protected]> Date: Thu Jun 4 14:47:23 2026 +0000 AArch64: Avoid zeroing movprfx on MOV/FMOV A zeroing movprfx with merging MOV/FMOV should be avoided since they result in a read of the destination register - this introduces extra dependencies eventhough the read has no useful effect. Remove such patterns so that the zero value is created via MOV d0, 0. Update various tests. gcc: * config/aarch64/aarch64-sve.md: Remove zeroing movprfx of merging MOV gcc/testsuite: * gcc.target/aarch64/sve/acle/asm/dup_bf16.c: Update. * gcc.target/aarch64/sve/acle/asm/dup_f16.c: Update. * gcc.target/aarch64/sve/acle/asm/dup_f32.c: Update. * gcc.target/aarch64/sve/acle/asm/dup_f64.c: Update. * gcc.target/aarch64/sve/acle/asm/dup_s16.c: Update. * gcc.target/aarch64/sve/acle/asm/dup_s32.c: Update. * gcc.target/aarch64/sve/acle/asm/dup_s64.c: Update. * gcc.target/aarch64/sve/acle/asm/dup_s8.c: Update. * gcc.target/aarch64/sve/acle/asm/dup_u16.c: Update. * gcc.target/aarch64/sve/acle/asm/dup_u32.c: Update. * gcc.target/aarch64/sve/acle/asm/dup_u64.c: Update. * gcc.target/aarch64/sve/acle/asm/dup_u8.c: Update. * gcc.target/aarch64/sve/acle/asm/mul_s16.c: Update. * gcc.target/aarch64/sve/acle/asm/mul_s32.c: Update. * gcc.target/aarch64/sve/acle/asm/mul_s64.c: Update. * gcc.target/aarch64/sve/acle/asm/mul_s8.c: Update. * gcc.target/aarch64/sve/acle/asm/mul_u16.c: Update. * gcc.target/aarch64/sve/acle/asm/mul_u32.c: Update. * gcc.target/aarch64/sve/acle/asm/mul_u64.c: Update. * gcc.target/aarch64/sve/acle/asm/mul_u8.c: Update. * gcc.target/aarch64/sve/vcond_18.c: Update. * g++.target/aarch64/sve/dup_sel_5.C: Update. * g++.target/aarch64/sve/dup_sel_6.C: Update. Diff: --- gcc/config/aarch64/aarch64-sve.md | 29 ++++++++++++++++------ gcc/testsuite/g++.target/aarch64/sve/dup_sel_5.C | 2 +- gcc/testsuite/g++.target/aarch64/sve/dup_sel_6.C | 2 +- .../gcc.target/aarch64/sve/acle/asm/dup_bf16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/dup_f16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/dup_f32.c | 6 ++--- .../gcc.target/aarch64/sve/acle/asm/dup_f64.c | 6 ++--- .../gcc.target/aarch64/sve/acle/asm/dup_s16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/dup_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/dup_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/dup_s8.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/dup_u16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/dup_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/dup_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/dup_u8.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mul_s16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mul_s32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mul_s64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mul_s8.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mul_u16.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mul_u32.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mul_u64.c | 2 +- .../gcc.target/aarch64/sve/acle/asm/mul_u8.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c | 16 ++++++------ 24 files changed, 55 insertions(+), 42 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 9523b75441c4..4d67ad0dc875 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -8601,6 +8601,14 @@ ;; For the other instructions, using the element size is more natural, ;; so we do that for SEL as well. ;; +;; Avoid patterns that use a zeroing movprfx like: +;; +;; movprfx z0.s, p0/z, z0.s +;; fmov z0.s, p0/m, #C +;; +;; This creates a false dependency on z0 which can result in stalls. +;; The zeroing will be done via a movi d0, 0 which is cheaper. +;; (define_insn "*vcond_mask_<mode><vpred>" [(set (match_operand:SVE_ALL 0 "register_operand") (unspec:SVE_ALL @@ -8616,30 +8624,35 @@ [ w , vss , 0 , Upa ; * ] mov\t%0.<Vetype>, %3/m, #%I1 [ w , vss , Dz , Upa ; * ] mov\t%0.<Vetype>, %3/z, #%I1 [ w , Ufc , 0 , Upa ; * ] fmov\t%0.<Vetype>, %3/m, #%1 - [ ?w , Ufc , Dz , Upl ; yes ] movprfx\t%0.<Vetype>, %3/z, %0.<Vetype>\;fmov\t%0.<Vetype>, %3/m, #%1 [ ?&w , vss , w , Upa ; yes ] movprfx\t%0, %2\;mov\t%0.<Vetype>, %3/m, #%I1 [ ?&w , Ufc , w , Upa ; yes ] movprfx\t%0, %2\;fmov\t%0.<Vetype>, %3/m, #%1 } ) -;; Optimize selects between a duplicated scalar variable and another vector, -;; the latter of which can be a zero constant or a variable. Treat duplicates -;; of GPRs as being more expensive than duplicates of FPRs, since they -;; involve a cross-file move. +;; Optimize selects between a duplicated scalar variable and another vector. +;; Treat duplicates of GPRs as being more expensive than duplicates of FPRs +;; since they involve a cross-file move. +;; +;; Avoid patterns that use a zeroing movprfx like: +;; +;; movprfx z0.s, p0/z, z0.s +;; mov z0.s, p0/m, #C +;; +;; This creates a false dependency on z0 which can result in stalls. +;; The zeroing will be done via a movi d0, 0 which is cheaper. +;; (define_insn "@aarch64_sel_dup<mode>" [(set (match_operand:SVE_ALL 0 "register_operand") (unspec:SVE_ALL [(match_operand:<VPRED> 3 "register_operand") (vec_duplicate:SVE_ALL (match_operand:<VEL> 1 "register_operand")) - (match_operand:SVE_ALL 2 "aarch64_simd_reg_or_zero")] + (match_operand:SVE_ALL 2 "register_operand")] UNSPEC_SEL))] "TARGET_SVE" {@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ] [ ?w , r , 0 , Upl ; * ] mov\t%0.<Vetype>, %3/m, %<vwcore>1 [ w , w , 0 , Upl ; * ] mov\t%0.<Vetype>, %3/m, %<Vetype>1 - [ ??w , r , Dz , Upl ; yes ] movprfx\t%0.<Vetype>, %3/z, %0.<Vetype>\;mov\t%0.<Vetype>, %3/m, %<vwcore>1 - [ ?&w , w , Dz , Upl ; yes ] movprfx\t%0.<Vetype>, %3/z, %0.<Vetype>\;mov\t%0.<Vetype>, %3/m, %<Vetype>1 [ ??&w , r , w , Upl ; yes ] movprfx\t%0, %2\;mov\t%0.<Vetype>, %3/m, %<vwcore>1 [ ?&w , w , w , Upl ; yes ] movprfx\t%0, %2\;mov\t%0.<Vetype>, %3/m, %<Vetype>1 } diff --git a/gcc/testsuite/g++.target/aarch64/sve/dup_sel_5.C b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_5.C index 2fb903a91510..21bbf781f126 100644 --- a/gcc/testsuite/g++.target/aarch64/sve/dup_sel_5.C +++ b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_5.C @@ -15,4 +15,4 @@ foo (int32_t val) asm volatile ("" :: "w" (x)); } -/* { dg-final { scan-assembler {\tmovprfx\tz0\.s, p[0-7]/z, z0\.s\n\tmov\tz0\.s, p[0-7]/m, w[0-9]+\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz0\.s, p[0-7]/m, w[0-9]+\n} } } */ diff --git a/gcc/testsuite/g++.target/aarch64/sve/dup_sel_6.C b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_6.C index f2b0181bb82d..7db426bd81d0 100644 --- a/gcc/testsuite/g++.target/aarch64/sve/dup_sel_6.C +++ b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_6.C @@ -15,4 +15,4 @@ foo (float val) asm volatile ("" :: "w" (x)); } -/* { dg-final { scan-assembler {\tmovprfx\tz0\.s, p[0-7]/z, z0\.s\n\tmov\tz0\.s, p[0-7]/m, s[0-9]+\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz[0-7]+\.s, p[0-7]/m, s[0-9]+\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_bf16.c index db47d849c5ff..fd9a654f42a7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_bf16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_bf16.c @@ -23,7 +23,7 @@ TEST_UNIFORM_ZD (dup_h4_bf16_m, svbfloat16_t, __bf16, /* ** dup_h4_bf16_z: -** movprfx z0\.h, p0/z, z0\.h +** movi d0, #?0 ** mov z0\.h, p0/m, h4 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c index 68e41ab15fd9..2f276a117012 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c @@ -151,7 +151,7 @@ TEST_UNIFORM_Z (dup_513_f16_z, svfloat16_t, z0 = svdup_f16_z (p0, 513)) /* ** dup_h4_f16_z: -** movprfx z0\.h, p0/z, z0\.h +** movi d0, #?0 ** mov z0\.h, p0/m, h4 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c index 29f4e520cf92..d5a8f6f4d6b7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c @@ -108,7 +108,7 @@ TEST_UNIFORM_ZD (dup_s4_f32_m, svfloat32_t, float, /* ** dup_1_f32_z: -** movprfx z0\.s, p0/z, z0\.s +** movi d0, #?0 ** fmov z0\.s, p0/m, #1\.0(?:e\+0)? ** ret */ @@ -127,7 +127,7 @@ TEST_UNIFORM_Z (dup_0_f32_z, svfloat32_t, /* ** dup_8_f32_z: -** movprfx z0\.s, p0/z, z0\.s +** movi d0, #?0 ** fmov z0\.s, p0/m, #8\.0(?:e\+0)? ** ret */ @@ -147,7 +147,7 @@ TEST_UNIFORM_Z (dup_513_f32_z, svfloat32_t, /* ** dup_s4_f32_z: -** movprfx z0\.s, p0/z, z0\.s +** movi d0, #?0 ** mov z0\.s, p0/m, s4 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c index 6501b86fb89c..f4313864f3f7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c @@ -108,7 +108,7 @@ TEST_UNIFORM_ZD (dup_d4_f64_m, svfloat64_t, double, /* ** dup_1_f64_z: -** movprfx z0\.d, p0/z, z0\.d +** movi d0, #?0 ** fmov z0\.d, p0/m, #1\.0(?:e\+0)? ** ret */ @@ -127,7 +127,7 @@ TEST_UNIFORM_Z (dup_0_f64_z, svfloat64_t, /* ** dup_8_f64_z: -** movprfx z0\.d, p0/z, z0\.d +** movi d0, #?0 ** fmov z0\.d, p0/m, #8\.0(?:e\+0)? ** ret */ @@ -147,7 +147,7 @@ TEST_UNIFORM_Z (dup_513_f64_z, svfloat64_t, /* ** dup_d4_f64_z: -** movprfx z0\.d, p0/z, z0\.d +** movi d0, #?0 ** mov z0\.d, p0/m, d4 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c index 5bcd3b457517..66b45ef3277d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c @@ -950,7 +950,7 @@ TEST_UNIFORM_Z (dup_0_s16_z, svint16_t, /* ** dup_w0_s16_z: -** movprfx z0\.h, p0/z, z0\.h +** movi d0, #?0 ** mov z0\.h, p0/m, w0 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c index b9cb1e5883d7..2337c370801b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c @@ -918,7 +918,7 @@ TEST_UNIFORM_Z (dup_0_s32_z, svint32_t, /* ** dup_w0_s32_z: -** movprfx z0\.s, p0/z, z0\.s +** movi d0, #?0 ** mov z0\.s, p0/m, w0 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c index e63bcf225d7d..de702273af85 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c @@ -918,7 +918,7 @@ TEST_UNIFORM_Z (dup_0_s64_z, svint64_t, /* ** dup_x0_s64_z: -** movprfx z0\.d, p0/z, z0\.d +** movi d0, #?0 ** mov z0\.d, p0/m, x0 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c index 66c8c92e27cf..c984eeb51c44 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c @@ -284,7 +284,7 @@ TEST_UNIFORM_Z (dup_0_s8_z, svint8_t, /* ** dup_w0_s8_z: -** movprfx z0\.b, p0/z, z0\.b +** movi d0, #?0 ** mov z0\.b, p0/m, w0 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c index 284d0476a9d3..0825a1503add 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c @@ -950,7 +950,7 @@ TEST_UNIFORM_Z (dup_0_u16_z, svuint16_t, /* ** dup_w0_u16_z: -** movprfx z0\.h, p0/z, z0\.h +** movi d0, #?0 ** mov z0\.h, p0/m, w0 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c index 77f39cc267b5..3416ff2808ef 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c @@ -918,7 +918,7 @@ TEST_UNIFORM_Z (dup_0_u32_z, svuint32_t, /* ** dup_w0_u32_z: -** movprfx z0\.s, p0/z, z0\.s +** movi d0, #?0 ** mov z0\.s, p0/m, w0 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c index 385b427f4972..f31648ce2eb7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c @@ -918,7 +918,7 @@ TEST_UNIFORM_Z (dup_0_u64_z, svuint64_t, /* ** dup_x0_u64_z: -** movprfx z0\.d, p0/z, z0\.d +** movi d0, #?0 ** mov z0\.d, p0/m, x0 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c index 8f2be55f23dc..bebb62a01d26 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c @@ -284,7 +284,7 @@ TEST_UNIFORM_Z (dup_0_u8_z, svuint8_t, /* ** dup_w0_u8_z: -** movprfx z0\.b, p0/z, z0\.b +** movi d0, #?0 ** mov z0\.b, p0/m, w0 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c index 4148097cc63c..fb680a909230 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c @@ -333,7 +333,7 @@ TEST_UNIFORM_Z (mul_1op1_s16_z_tied2, svint16_t, /* ** mul_1op1n_s16_z: -** movprfx z0\.h, p0/z, z0\.h +** movi d0, #?0 ** mov z0\.h, p0/m, w0 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c index 2c53e3f14d64..fac7fa9c2796 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c @@ -343,7 +343,7 @@ TEST_UNIFORM_Z (mul_1op1_s32_z_tied2, svint32_t, /* ** mul_1op1n_s32_z: -** movprfx z0\.s, p0/z, z0\.s +** movi d0, #?0 ** mov z0\.s, p0/m, w0 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c index 55342a13f8bd..a7ddf7efae8d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c @@ -342,7 +342,7 @@ TEST_UNIFORM_Z (mul_1op1_s64_z_tied2, svint64_t, /* ** mul_1op1n_s64_z: -** movprfx z0\.d, p0/z, z0\.d +** movi d0, #?0 ** mov z0\.d, p0/m, x0 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c index 786a424eeead..e85ed420ddd1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c @@ -333,7 +333,7 @@ TEST_UNIFORM_Z (mul_1op1_s8_z_tied2, svint8_t, /* ** mul_1op1n_s8_z: -** movprfx z0\.b, p0/z, z0\.b +** movi d0, #?0 ** mov z0\.b, p0/m, w0 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c index ed08635382d5..6f193bccbb6b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c @@ -314,7 +314,7 @@ TEST_UNIFORM_Z (mul_1op1_u16_z_tied2, svuint16_t, /* ** mul_1op1n_u16_z: -** movprfx z0\.h, p0/z, z0\.h +** movi d0, #?0 ** mov z0\.h, p0/m, w0 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c index f82ac4269e8f..c1638ae1645e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c @@ -314,7 +314,7 @@ TEST_UNIFORM_Z (mul_1op1_u32_z_tied2, svuint32_t, /* ** mul_1op1n_u32_z: -** movprfx z0\.s, p0/z, z0\.s +** movi d0, #?0 ** mov z0\.s, p0/m, w0 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c index 9f1bfff5fd2f..1161871483b6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c @@ -335,7 +335,7 @@ TEST_UNIFORM_Z (mul_1op1_u64_z_tied2, svuint64_t, /* ** mul_1op1n_u64_z: -** movprfx z0\.d, p0/z, z0\.d +** movi d0, #?0 ** mov z0\.d, p0/m, x0 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c index b2c1edf5ff82..48593487f8c4 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c @@ -314,7 +314,7 @@ TEST_UNIFORM_Z (mul_1op1_u8_z_tied2, svuint8_t, /* ** mul_1op1n_u8_z: -** movprfx z0\.b, p0/z, z0\.b +** movi d0, #?0 ** mov z0\.b, p0/m, w0 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c index bd83e4c377d0..40451b1fb567 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c @@ -31,14 +31,14 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-9]+/z, #-16128\n} 1 } } */ /* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-9]+, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ -/* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.s), (p[0-7])/z, \1\n\tfmov\t\1, \2/m, #2\.0(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.s), (p[0-7])/z, \1\n\tfmov\t\1, \2/m, #1\.25(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.s), (p[0-7])/z, \1\n\tfmov\t\1, \2/m, #-4\.0(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.s), (p[0-7])/z, \1\n\tfmov\t\1, \2/m, #-2\.5(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m, #2\.0(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m, #1\.25(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m, #-4\.0(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m, #-2\.5(?:e[+]0)?\n} } } */ /* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-9]+, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ -/* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.d), (p[0-7])/z, \1\n\tfmov\t\1, \2/m, #2\.0(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.d), (p[0-7])/z, \1\n\tfmov\t\1, \2/m, #1\.25(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.d), (p[0-7])/z, \1\n\tfmov\t\1, \2/m, #-4\.0(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.d), (p[0-7])/z, \1\n\tfmov\t\1, \2/m, #-2\.5(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m, #2\.0(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m, #1\.25(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m, #-4\.0(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\tz[0-9]+\.s, p[0-9]+/m, #-2\.5(?:e[+]0)?\n} } } */ /* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-9]+, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
