The branch 'riscv/heads/gcc-15-with-riscv-opts' was updated to point to:
249d80fd0152... Fixup merge conflict
It previously pointed to:
b6484e089a79... [PATCH v2] RISC-V: Fix type of CFA during stack probe [PR12
Diff:
!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
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b6484e0... [PATCH v2] RISC-V: Fix type of CFA during stack probe [PR12
461b0b5... [RISC-V][PR target/122147] Avoid creating (subreg (mem)) in
2db1ef3... [PR target/118945][PATCH v3] RISC-V: Add 'prefer_agnostic'
e700c45... [RISC-V][PR rtl-optimization/121937] Don't call neg_poly_in
9d190d7... [PATCH v2] RISC-V: fix __builtin_round NaN handling [PR tar
6a38eb3... [RISC-V][PR target/122051] Fix pmode_reg_or_uimm5_operand f
ebdc1ec... [RISC-V][PR target/122106] Add missing predicate on crc exp
1574bc0... [PATCH][PR target/121778] RISC-V: Improve rotation detectio
5f49331... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
60de8ea... RISC-V: Add missing define_insn_reservation to tt-ascalon-d
884e3df... [RISC-V][PR target/121983] Fix unprotected REGNO invocation
1187e6c... RISC-V: Improve slide patterns recognition
dbcc54f... RISC-V: Only Save/Restore required registers for ILP32E/LP6
4857769... [RISC-V] Optimize clear-lowest-set-bit sequence when ctz is
13b15bd... RISC-V: Correct lmul estimation
f59c712... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
81bd1f8... [PR tree-optimization/58727] Don't over-simplify constants`
a4d78f5... RISC-V: Add test for vec_duplicate + vwmulu.vv signed combi
844b15e... RISC-V: Add test for vec_duplicate + vwsubu.vv signed combi
a787d41... RISC-V: Add test for vec_duplicate + vwaddu.vv signed combi
810e3cb... RISC-V: Combine vec_duplicate + vwaddu.vv to vwaddu.vx on G
d664115... RISC-V: Allow profiles input in '--with-arch' option.
80e5424... RISC-V: Configure Profiles definitions in the definition fi
bd0a5ad... RISC-V: Imply zicsr for sdtrig and ssstrict extensions.
d3380ef... Widening-Mul: Refine build_and_insert_cast when rhs is cast
baa7f67... RISC-V: Fix vendor intrinsic tests for disabled multilib co
eb150f1... Fix latent LRA bug
3cff286... RISC-V: Support vnclip idiom testcase [PR120378]
df708cb... Match: Support SAT_TRUNC variant NARROW_CLIP
f667087... [RISC-V] Adjust ABI specification in recently added Andes t
074e09c... RISC-V: Suppress cross CC sibcall optimization from vector
7ab6db6... RISC-V: Add min/max patterns for ifcvt.
18ef461... ifcvt: Clarify if_info.original_cost.
8d2c2f1... RISC-V: Fix can_find_related_mode_p for VLS types
0ce2bb9... RISC-V: Fix typo in tt-ascalon-d8's pipeline description [P
8a5b972... RISC-V: Add pattern for vector-scalar single widening float
902064d... RISC-V: Add pattern for vector-scalar dual widening floatin
e1015d1... RISC-V: Add pattern for vector-scalar single widening float
e386a02... RISC-V: Add pattern for vector-scalar widening floating-poi
d2fb01e... RISC-V: Adjust tt-ascalon-d8 branch cost
6a30568... RISC-V: Add pattern for vector-scalar single-width floating
c98cdf0... RISC-V: Add pattern for vector-scalar single-width floating
4405f45... RISC-V: Add pattern for vector-scalar single-width floating
8b5fd4a... RISC-V: Add pattern for vector-scalar widening floating-poi
ed329bd... RISC-V: Add patterns for vector-scalar IEEE floating-point
43c740c... gcc: introduce the dep_fusion pass
ff229c4... RISC-V: Add support for the XAndesvdot ISA extension.
a15da95... [RISC-V] Fix ordering of pipeline models
9d7df5e... RISC-V: Add support for the XAndesvpackfph ISA extension.
b6c74f5... RISC-V: Add test for vec_duplicate + vnmsub.vv unsigned com
268cd08... RISC-V: Add test for vec_duplicate + vnmsub.vv signed combi
28bdf2d... RISC-V: Combine vec_duplicate + vnmsub.vv to vnmsub.vx on G
268c33d... dep_fusion: Fix if target does not have macro fusion [PR121
d42f020... gcc: introduce the dep_fusion pass
9d2433d... RISC-V: Add support for the XAndesvsintload ISA extension.
85a9f5d... RISC-V: Add support for the XAndesvbfhcvt ISA extension.
ea75e24... RISC-V: Add tt-ascalon-d8 pipeline description
7d822b5... [RISC-V] Adjust recently added test
dfe99cc... RISC-V: Combine vec_duplicate + vmadd.vv to vmadd.vx on GR2
a53e328... RISC-V: Allow errors to be suppressed when parsing architec
a051078... RISC-V: Adjust the vmacc.vx combine test cases
8596562... RISC-V: Add test for vec_duplicate + vmadd.vv unsigned comb
0dbb2be... RISC-V: Add test for vec_duplicate + vmadd.vv signed combin
0fa5b5b... RISC-V: Use correct target in expand_vec_perm [PR121780].
94e902f... RISC-V: Always register vector built-in functions during LT
aeb3508... RISC-V: Fix extension subset check in riscv_can_inline_p
104ddd6... RISC-V: Add support for the XAndesbfhcvt ISA extension.
31b8d5c... RISC-V: Add support for the XAndesperf ISA extension.
e537a2a... RISC-V: Add basic XAndes vendor extension support.
f58e67e... RISC-V: Add pattern for vector-scalar floating-point max
d64f510... [RISC-V][PR target/121213] Avoid unnecessary sign extension
72be713... RISC-V: Fix is_vlmax_len_p and use for strided ops.
d4a5d8d... RISC-V: Handle overlap in expand_vec_perm PR121742.
99fdaa3... RISC-V: Add Zbb extension sext testcase.
2c89d44... RISC-V: Update Zba 'shNadd.uw' testcase.`
847f878... RISC-V: Remove unused print_ext_doc_entry function [NFC]
cef6a88... [RISC-V] Improve initial RTL generation for SImode adds on
8986a67... RISC-V: Add test case for unsigned scalar SAT_MUL form 4
8d15c1c... RISC-V: Add patterns for vector-scalar IEEE floating-point
f356439... RISC-V: Add test for vec_duplicate + vnmsac.vv unsigned com
3ce39b5... RISC-V: Add test for vec_duplicate + vnmsac.vv signed combi
79f538e... RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on G
361aa8a... RISC-V: Add pattern for vector-scalar floating-point min
8ac6795... Remove xfail marker on RISC-V test
db540fc... RISC-V: testsuite: Fix vf_vfmul and vf_vfrdiv
25fd42d... More RISC-V testsuite hygiene
41c322c... [committed] RISC-V Testsuite hygiene
57a554e... [PATCH] RISC-V: Add pattern for reverse floating-point divi
06cef8c... [PATCH] RISC-V: Add pattern for vector-scalar single-width
d5c2c56... Fix RISC-V bootstrap
e91a6ef... RISC-V: Add test for vec_duplicate + vmacc.vv unsigned comb
4ad94f9... RISC-V: Add test for vec_duplicate + vmacc.vv signed combin
6462c2b... RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2
207f3a0... RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE mac
778fa3c... Fix invalid right shift count with recent ifcvt changes
dd31e96... [PR rtl-optimization/120553] Improve selecting between cons
5ae9896... RISC-V: Add testcase for scalar unsigned SAT_MUL form 3
9039453... RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh
580cd2f... [PR target/121213] Avoid unnecessary constant load in amosw
52908a9... regrename: treat writes as reads for fused instruction pair
a3c303d... ira: tie output allocnos for fused instruction pairs
3500479... [PATCH] RISC-V: Fix block matching in arch-canonicalize [PR
ad4ac3a... RISC-V: Update the comments of vx combine [NFC]
d7f81bc... RISC-V: Add missed DONE for vx combine pattern [NFC]
87299ec... RISC-V: MIPS prefetch extensions for MIPS RV64 P8700 and ca
97fa0ab... [PR target/119275][RISC-V] Avoid calling gen_lowpart in cas
7eb565a... [RISC-V][PR target/121531] Cover missing insn types in p400
bea502e... [RISC-V][PR target/121160] Avoid bogus force_reg call
578b687... [RISC-V][PR target/121113] Handle HFmode in various insn re
652f761... RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm com
c4a2f91... RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on G
e8ade79... RISC-V: Expand const_vector with 2 elts per pattern.
bfbe3e2... Improve initial code generation for addsi/adddi
a680633... Don't run tests requiring "B" on designs without "B"
f2e85de... RISC-V: Add testcase for scalar unsigned SAT_MUL form 2
01e5068... RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost
2886eee... RISC-V: Read extension data from riscv-ext*.def for arch-ca
fb5cc25... RISC-V: Support -march=unset
c4b6960... RISC-V: Fix scalar code-gen of unsigned SAT_MUL
893783a... RISC-V: Add testcases for signed avg ceil vx combine
7212548... RISC-V: Adding H to the canonical order [PR121312]
295de2b... RISC-V: Add testcases for unsigned avg ceil vx combine.
6de1b95... RISC-V: Generate -mcpu and -mtune options from riscv-cores.
2004f04... RISC-V: Remove use of structured binding to fix compiler wa
ef80db6... RISC-V: Add test cases for mul based unsigned scalar SAT_MU
c56d054... RISC-V: Add test case for vaadd.vx combine polluting VXRM
5ab446e... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
2f106c8... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
f0cb00f... RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2
fe3c30c... RISC-V: Fix another vf FP16 combine run test failures
9ecef70... RISC-V: riscv-ext.def: Add allocated group IDs and group bi
7614ace... RISC-V: Prepare dynamic LMUL heuristic for SLP.
2425ba0... RISC-V: Remove user-level interrupts
2f60948... RISC-V: Add support for resumable non-maskable interrupt (R
cce3932... riscv: testsuite: Fix misalignment check.
b5208ba... RISC-V: Add test case for vx combine polluting VXRM
25a1f1c... RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr
f8aecfa... RISC-V: Rework broadcast handling [PR121073].
72792ff... RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.
481930e... Change bellow in comments to below
6acf236... [RISC-V] Restrict generic-vector-ooo DFA
a142db0... [RISC-V] Add missing insn types to xiangshan.md and mips-p8
cb58cee... RISC-V: Add test for vec_duplicate + vaaddu.vv combine for
3801ce3... RISC-V: Allow VLS DImode for sat_op vx DImode pattern
8ad7351... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
db2be63... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
1180dc9... RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on G
da34ac6... RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and
fe560be... RISC-V: Refine the test case for vector avg_floor and avg_c
b5c8d2c... RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg
c1c5a14... [PATCH] RISC-V: Vector-scalar widening negate-multiply-(sub
83f4ccc... [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro
4a64dc5... RISC-V: Support RVVDImode for avg3_ceil auto vect
201f84e... RISC-V: Fix vsetvl merge rule.
b51791e... RISC-V: Refine the scalar SAT_* test cases
87b354e... RISC-V: Support RVVDImode for avg3_floor auto vect
cd70128... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
33927e2... RISC-V: Add testcase for rv32 SAT_MUL from uint64
5bd4d8f... [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtrac
65c1a52... RISC-V: Add testcases for unsigned vector SAT_SUB form 11 a
7a0843f... RISC-V: Make zero-stride load broadcast a tunable.
88c7db0... [RISC-V] Detect new fusions for RISC-V
0359291... RISCV: Remove the v extension requirement for sat scalar ru
78f75ae... RISC-V: Add test for vec_duplicate + vssub.vv combine case
cf44911... RISC-V: Add test for vec_duplicate + vssub.vv combine case
39b976b... RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2
2fae7fb... [PATCH] RISC-V: Enable zvfh for vector-scalar half-float ru
474878a... [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB
c4a4fc2... [RISC-V][PR target/120642] Avoid propagating constant AVL f
7fec806... RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
a051974... RISC-V: Do not use vsetivli for THeadVector.
f1e49af... RISC-V: Ignore non-types in builtin function hash.
5eef4d4... [committed][RISC-V] Fix testsuite fallout from check-functi
5ff0fa8... RISC-V: Add test cases for unsigned scalar SAT_MUL from uin
7f7cfac... RISC-V: Implement unsigned scalar SAT_MUL from uint128_t
9f54e4a... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
68c9a44... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
24e2641... RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2
67e71a6... [RISC-V] Add basic instrumentation to fusion detection
38a324f... RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
f158bcd... Refactor record_function_versions.
6025fc8... [RISC-V][PR target/118886] Refine when two insns are signal
701108e... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
f11124f... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
d0ad00f... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
88bb8a1... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
1dea554... RISC-V: Reconcile the existing test due to cost model chang
10c230a... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
a141780... RISC-V: Ignore -Oz for most rvv testcase [NFC]
a1a50b7... RISC-V: Primary vector pipeline model for sifive 7 series
05aa239... RISC-V: Adding B ext, fp16 and missing scalar instruction t
c196968... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
dfeac1a... RISC-V: Refactor the function bitmap_union_of_preds_with_en
6391d9c... RISC-V: Add pipeline-checker script
2db5155... [RISC-V][PR target/119971] Avoid losing shift count masking
eeae027... RISC-V: update prepare_ternary_operands to handle vector-sc
cc4fb3d... RISC-V: Fix build issue
c2dbb6f... RISC-V: Add comment and reorder the the include files in ri
e5839aa... RISC-V: Add Profiles RVA/B23S64 support.
9cc8b2f... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
1908d07... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
31c1453... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
f6a7400... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
9790216... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
0708ff5... RISC-V: Fix ICE for expand_select_vldi [PR120652]
22cd180... [RISC-V] Force several tests to use rocket tuning
540833e... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
8b010c6... RISC-V: Add test for vec_duplicate + vminu.vv combine case
78fafe5... RISC-V: Add test for vec_duplicate + vminu.vv combine case
67cbecb... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
f058ab9... RISC-V: Add generic tune as default.
ce6cc7d... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
8831a31... RISC-V: Adding cost model for zilsd
ca1bd59... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
ef720a8... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
7822896... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
54c7cce... [PATCH v1] RISC-V: Use scratch reg for loop control
23e97c4... RISC-V: Add -fno-pie flags to testcases
a769777... RISC-V: Refine VX combine test case 0 to avoid code duplica
3f10401... RISC-V: Update Profiles string in RV23.
77daa1d... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
9bdce6a... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
79a830c... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
100225f... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
33ba9ce... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
2f36a39... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
e432c75... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
57605a0... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
b81a42d... RISC-V: Prevent speculative vsetvl insn scheduling
9b9f51a... RISC-V: Add patterns for vector-scalar negate-(multiply-add
bcc6f4d... RISC-V: testsuite: fix an obvious build error
da17e1a... RISC-V: Regen riscv-ext.texi [NFC]
4dc4609... RISC-V: Add test for vec_duplicate + vremu.vv combine case
b7fcd19... RISC-V: Add test for vec_duplicate + vremu.vv combine case
9f12259... RISC-V: Reconcile the existing test for vremu.vx combine
f8735a7... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
cd4527f... [RISC-V] Enable more if-conversion on RISC-V
ffc1e5f... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
e517ecc... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
75e94f9... RISC-V: Reconcile the existing test for vrem.vx combine
fc92dba... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
a28e5e9... RISC-V: frm/mode-switch: robustify call_insn backtracking [
d901e45... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
c9ffb42... RISC-V: frm/mode-switch: remove dubious frm edge insertion
90e4cf3... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
6d8659f... [RISC-V] Handle 32bit operands in condition for conditional
0c20acf... [to-be-committed][RISC-V] Handle 32bit operands in conditio
2babc25... RISC-V: Reconcile the existing test for vdivu.vx combine
06989c6... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
8b34fd6... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
00dfa94... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
1b14356... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
6d50409... [RISC-V] Improve signed division by 2^n
db0fd05... RISC-V: Don't use structured binding in riscv-common.cc
9d4fbe2... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
3f414c7... [RISC-V] Improve sequences to generate -1, 1 in some cases.
cac514f... RISC-V: Support Ssu64xl extension.
d4122be... RISC-V: Support Sstvecd extension.
a19daf1... RISC-V: Support Sstvala extension.
f1f241c... RISC-V: Support Sscounterenw extension.
32ec9d5... RISC-V: Support Ssccptr extension.
0eb29ee... RISC-V: Support Smrnmi extension.
97dd38d... RISC-V: Support Sm/scsrind extensions.
9fe0b82... RISC-V: Update extension defination.
1fcc389... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
9602b05... [PATCH v2] RISC-V: Add svbare extension.
9c37d40... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
eb0269f... RISC-V: Add Shlcofideleg extension.
d7e7745... RISC-V: Reconcile the existing test for vdiv.vx combine
f17fbff... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
1682561... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
7be061f... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
5143fa4... RISC-V: Use helper function to get FPR to VR move cost
a562773... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
13ecc32... [PATCH] RISC-V: Add smcntrpmf extension.
08dcca3... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
89fef47... RISC-V: Implement full-featured iterator for riscv_subset_l
117afb6... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
7aae85d... RISC-V: Fix line too long format issue for autovect.md [NFC
4c37e89... RISC-V: Add test cases for avg_ceil vaadd implementation
cc1e00a... RISC-V: Reconcile the existing test for avg_ceil
6ff9c6e... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
8e91c55... RISC-V: Add minimal support of double trap extension 1.0
a10973b... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
039c211... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
88ecbc9... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
d39c700... RISC-V: Avoid division by zero in check_builtin_call [PR120
9ee44a0... RISC-V: Add test cases for avg_floor vaadd implementation
4ae3428... RISC-V: Reconcile the existing test for avg_floor
237e6f7... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
81eda40... [RISC-V] Add andi+bclr synthesis
c6a7e11... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
e07c7bf... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
fbe28ca... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
a4b7bcc... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
0cc5036... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
975f447... [RISC-V] shift+and+shift for logical and synthesis
100d029... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
a7b8a3b... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
9b8b257... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
eb8bd08... RISC-V: Support CPUs in -march.
3fef165... RISC-V: Add autovec mode param.
92a2798... RISC-V: Default-initialize variable.
796346e... RISC-V: Fix some dynamic LMUL costing.
60b781c... [RISC-V] Clear both upper and lower bits using 3 shifts
cc441a5... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
9611a54... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
192a7b5... [RISC-V] Clear high or low bits using shift pairs
dbf8782... [RISC-V] Improve (x << C1) + C2 split code
11150f3... [RISC-V][PR target/120368] Fix 32bit shift on rv64
6dee672... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
21d0d9a... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
5b1ded9... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
afd52cc... [RISC-V] Infrastructure of synthesizing logical AND with co
8257509... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
28eefd4... [PATCH v2 1/2] The following changes enable P8700 processor
1d00b29... [RISC-V] Avoid multiple assignments to output object
7c03b3a... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
c2b32db... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
b50fd63... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
cb21a95... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
796989b... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
2a0e5c6... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
7519537... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
9c9d994... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
5a901b1... [committed][RISC-V][PR target/120333] Remove bogus bext pat
70295d0... [RISC-V] Fix false positive from Wuninitialized
4de5851... RISC-V: Fix the warning of temporary object dangling refere
d43f655... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
02bfc18... RISC-V: Support Zilsd code gen
7854069... RISC-V: Add new operand constraint: cR
1403a25... [RISC-V] Fix ICE due to bogus use of gen_rtvec
c604c4f... [RISC-V] Avoid setting output object more than once in IOR/
4fb180c... RISC-V: Since the loop increment i++ is unreachable, the lo
ac33469... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
eec3a8a... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
dbdc116... Make end_sequence return the insn sequence
441da7e... RISC-V: Reuse test name for vx combine test data [NFC]
bd201c2... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
b6b31d5... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
2b63862... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
9cb277b... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
33e732c... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
5cf4aac... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
3970b35... RISC-V: Adjust vx combine test case to avoid name conflict
92dc846... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
55d8883... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
b02bab5... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
97741b4... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
4c43ce7... RISC-V: Add augmented hypervisor series extensions.
7c5bef0... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
20b55d9... RISC-V: Regen riscv-ext.opt.urls
7188430... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
ae541e4... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
c3b7684... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
6791d38... RISC-V: Introduce riscv_ext_info_t to hold extension metada
007dc74... RISC-V: Adjust riscv_can_inline_p
9265ed2... RISC-V: Generate extension table in documentation from risc
2375a31... RISC-V: Use riscv-ext.def to generate target options and va
d826fd8... RISC-V: Introduce riscv-ext*.def to define extensions
f539d0c... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
95e14bf... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
3ddefe7... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
b507680... RISC-V: Support for zilsd and zclsd extensions.
5e925df... testsuite: Fix RISC-V arch-52.c format issue.
da9d35a... RISC-V: Support RISC-V Profiles 23.
3c88742... RISC-V: Support RISC-V Profiles 20/22.
19ca071... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
5f42690... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
0c8f5d9... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
272ea7f... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
e05923c... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
583ff95... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
0ec8a28... RISC-V: Separate the test running of rvv vx_vf
aec5f9a... [RISC-V][PR target/120137][PR target/120154] Don't create o
c62f976... [PATCH] RISC-V: Minimal support for zama16b extension.
9bd3a6f... [RISC-V] Avoid unnecessary andi with -1 argument
42b7dad... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
7f8e2da... [PATCH] RISC-V: Recognized svadu and svade extension
6846802... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
1c8565a... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
ce5cf7e... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
2ceff77... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
988ed28... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
d2f7845... RISC-V: Add gr2vr cost helper function
b535374... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
af726b8... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
c8b0971... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
c43ec17... [V2][RISC-V] Trivial permutation constant derivation
7e41041... [RISC-V] Adjust rvv tests after recent jump threading chang
932cc96... [PATCH] RISC-V: Implment H modifier for printing the next r
33847ab... [to-be-committed][RISC-V] Adjust testcases and finish regis
3e21220... RISC-V: Remove unnecessary frm restore volatile define_insn
48fb726... RISC-V: Allow different dynamic floating point mode to be m
d7b5819... RISC-V: Fix missing implied Zicsr from Zve32x
69d67f1... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
e60a6c0... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
0b7aff4... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
1e94dbc... RISC-V: Extract vector stepped for expand_const_vector [NFC
c9a253d... RISC-V: Extract vector duplicate for expand_const_vector [N
ab1776f... RISC-V: Extract vec_series for expand_const_vector [NFC]
430dbc8... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
39c9a71... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
4f89088... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
08180c3... [riscv] vec_dup immediate constants in pred_broadcast expan
e4e5214... [RISC-V][PR target/119865] Don't free ggc allocated memory
9acc28f... [RISC-V][PR target/118410] Improve code generation for some
aec35ca... [RISC-V] Fix missed bext discovery
3f0700b... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
93b0c20... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
d1f60eb... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
Summary of changes (added commits):
-----------------------------------
249d80f... Fixup merge conflict
3164c5b... [PATCH v2] RISC-V: Fix type of CFA during stack probe [PR12
1bb8c89... [RISC-V][PR target/122147] Avoid creating (subreg (mem)) in
496c7a5... [PR target/118945][PATCH v3] RISC-V: Add 'prefer_agnostic'
d644cc4... [RISC-V][PR rtl-optimization/121937] Don't call neg_poly_in
6f8475e... [PATCH v2] RISC-V: fix __builtin_round NaN handling [PR tar
3f7572a... [RISC-V][PR target/122051] Fix pmode_reg_or_uimm5_operand f
9d127d4... [RISC-V][PR target/122106] Add missing predicate on crc exp
6361cff... [PATCH][PR target/121778] RISC-V: Improve rotation detectio
6c35a54... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
e4ec87a... RISC-V: Add missing define_insn_reservation to tt-ascalon-d
772ec4d... [RISC-V][PR target/121983] Fix unprotected REGNO invocation
ac481eb... RISC-V: Improve slide patterns recognition
e093517... RISC-V: Only Save/Restore required registers for ILP32E/LP6
a462168... [RISC-V] Optimize clear-lowest-set-bit sequence when ctz is
0fb8269... RISC-V: Correct lmul estimation
8f51044... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
d391c19... [PR tree-optimization/58727] Don't over-simplify constants`
d9799b7... RISC-V: Add test for vec_duplicate + vwmulu.vv signed combi
ed33bb7... RISC-V: Add test for vec_duplicate + vwsubu.vv signed combi
9f2e8d7... RISC-V: Add test for vec_duplicate + vwaddu.vv signed combi
5ce29de... RISC-V: Combine vec_duplicate + vwaddu.vv to vwaddu.vx on G
45c4950... RISC-V: Allow profiles input in '--with-arch' option.
dc6066d... RISC-V: Configure Profiles definitions in the definition fi
a9fa032... RISC-V: Imply zicsr for sdtrig and ssstrict extensions.
ac187b4... Widening-Mul: Refine build_and_insert_cast when rhs is cast
dc3a35d... RISC-V: Fix vendor intrinsic tests for disabled multilib co
b711ad1... RISC-V: Support vnclip idiom testcase [PR120378]
be2fa61... Match: Support SAT_TRUNC variant NARROW_CLIP
c718eba... [RISC-V] Adjust ABI specification in recently added Andes t
e911256... RISC-V: Suppress cross CC sibcall optimization from vector
a799d7e... RISC-V: Add min/max patterns for ifcvt.
437086c... ifcvt: Clarify if_info.original_cost.
471cbcf... RISC-V: Fix can_find_related_mode_p for VLS types
f7fc258... RISC-V: Fix typo in tt-ascalon-d8's pipeline description [P
8aa4b28... RISC-V: Add pattern for vector-scalar single widening float
1bc0d7e... RISC-V: Add pattern for vector-scalar dual widening floatin
3b33628... RISC-V: Add pattern for vector-scalar single widening float
439ed14... RISC-V: Add pattern for vector-scalar widening floating-poi
6df8725... RISC-V: Adjust tt-ascalon-d8 branch cost
15a8b61... RISC-V: Add pattern for vector-scalar single-width floating
584fefa... RISC-V: Add pattern for vector-scalar single-width floating
446b49a... RISC-V: Add pattern for vector-scalar single-width floating
aecb3e4... RISC-V: Add pattern for vector-scalar widening floating-poi
c61162e... RISC-V: Add patterns for vector-scalar IEEE floating-point
51e7946... gcc: introduce the dep_fusion pass
2cae941... RISC-V: Add support for the XAndesvdot ISA extension.
c7c8a1c... [RISC-V] Fix ordering of pipeline models
9618ebc... RISC-V: Add support for the XAndesvpackfph ISA extension.
7024d02... RISC-V: Add test for vec_duplicate + vnmsub.vv unsigned com
e4bdcb6... RISC-V: Add test for vec_duplicate + vnmsub.vv signed combi
2a45294... RISC-V: Combine vec_duplicate + vnmsub.vv to vnmsub.vx on G
26cb012... dep_fusion: Fix if target does not have macro fusion [PR121
51ea80c... gcc: introduce the dep_fusion pass
0fa07d5... RISC-V: Add support for the XAndesvsintload ISA extension.
d0f27c9... RISC-V: Add support for the XAndesvbfhcvt ISA extension.
1d0225d... RISC-V: Add tt-ascalon-d8 pipeline description
de155f1... [RISC-V] Adjust recently added test
d7f71b9... RISC-V: Combine vec_duplicate + vmadd.vv to vmadd.vx on GR2
e48d1c1... RISC-V: Allow errors to be suppressed when parsing architec
1212411... RISC-V: Adjust the vmacc.vx combine test cases
6b003c1... RISC-V: Add test for vec_duplicate + vmadd.vv unsigned comb
496a710... RISC-V: Add test for vec_duplicate + vmadd.vv signed combin
988cbe7... RISC-V: Fix extension subset check in riscv_can_inline_p
361499b... RISC-V: Add support for the XAndesbfhcvt ISA extension.
b9e9e15... RISC-V: Add support for the XAndesperf ISA extension.
dbf2889... RISC-V: Add basic XAndes vendor extension support.
f641c4e... RISC-V: Add pattern for vector-scalar floating-point max
67dbe01... [RISC-V][PR target/121213] Avoid unnecessary sign extension
fdebd31... RISC-V: Fix is_vlmax_len_p and use for strided ops.
d0d31e8... RISC-V: Add Zbb extension sext testcase.
7795ac1... RISC-V: Update Zba 'shNadd.uw' testcase.`
d884306... RISC-V: Remove unused print_ext_doc_entry function [NFC]
2dedddc... [RISC-V] Improve initial RTL generation for SImode adds on
fa9c523... RISC-V: Add test case for unsigned scalar SAT_MUL form 4
4aa0de6... RISC-V: Add patterns for vector-scalar IEEE floating-point
8f93196... RISC-V: Add test for vec_duplicate + vnmsac.vv unsigned com
ac780e5... RISC-V: Add test for vec_duplicate + vnmsac.vv signed combi
ac70276... RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on G
95eae80... RISC-V: Add pattern for vector-scalar floating-point min
e8a6ad9... Remove xfail marker on RISC-V test
49f14af... RISC-V: testsuite: Fix vf_vfmul and vf_vfrdiv
e9e867c... More RISC-V testsuite hygiene
4f5bdd8... [committed] RISC-V Testsuite hygiene
772b431... [PATCH] RISC-V: Add pattern for reverse floating-point divi
1aaea6f... [PATCH] RISC-V: Add pattern for vector-scalar single-width
1f1819d... Fix RISC-V bootstrap
5db7105... RISC-V: Add test for vec_duplicate + vmacc.vv unsigned comb
5211e78... RISC-V: Add test for vec_duplicate + vmacc.vv signed combin
3c52fed... RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2
6fab0f7... RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE mac
6df4b4a... Fix invalid right shift count with recent ifcvt changes
25c8c3f... [PR rtl-optimization/120553] Improve selecting between cons
f3ecc8f... RISC-V: Add testcase for scalar unsigned SAT_MUL form 3
730d65f... RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh
4289250... [PR target/121213] Avoid unnecessary constant load in amosw
03f054b... regrename: treat writes as reads for fused instruction pair
84a65e1... ira: tie output allocnos for fused instruction pairs
7213d9e... [PATCH] RISC-V: Fix block matching in arch-canonicalize [PR
5c665ae... RISC-V: Update the comments of vx combine [NFC]
b8dd150... RISC-V: Add missed DONE for vx combine pattern [NFC]
2d4fd27... RISC-V: MIPS prefetch extensions for MIPS RV64 P8700 and ca
fa26ece... [PR target/119275][RISC-V] Avoid calling gen_lowpart in cas
437a2f8... [RISC-V][PR target/121531] Cover missing insn types in p400
c34fb13... [RISC-V][PR target/121160] Avoid bogus force_reg call
1052884... [RISC-V][PR target/121113] Handle HFmode in various insn re
3077c27... RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm com
bde7aad... RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on G
fd71e9c... RISC-V: Expand const_vector with 2 elts per pattern.
68d02f3... Improve initial code generation for addsi/adddi
892eb72... Don't run tests requiring "B" on designs without "B"
6e4f4c4... RISC-V: Add testcase for scalar unsigned SAT_MUL form 2
c6bbc3b... RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost
ddfc95f... RISC-V: Read extension data from riscv-ext*.def for arch-ca
eb234fe... RISC-V: Support -march=unset
f41f5a9... RISC-V: Fix scalar code-gen of unsigned SAT_MUL
f0d5653... RISC-V: Add testcases for signed avg ceil vx combine
96bd260... RISC-V: Adding H to the canonical order [PR121312]
b4f7554... RISC-V: Add testcases for unsigned avg ceil vx combine.
8d74998... RISC-V: Generate -mcpu and -mtune options from riscv-cores.
f32b334... RISC-V: Remove use of structured binding to fix compiler wa
dfd6241... RISC-V: Add test cases for mul based unsigned scalar SAT_MU
c2af6e2... RISC-V: Add test case for vaadd.vx combine polluting VXRM
459c892... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
361de94... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
a814033... RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2
c448775... RISC-V: Fix another vf FP16 combine run test failures
e76fe58... RISC-V: riscv-ext.def: Add allocated group IDs and group bi
32f1186... RISC-V: Prepare dynamic LMUL heuristic for SLP.
705d6ff... RISC-V: Remove user-level interrupts
6522e2f... RISC-V: Add support for resumable non-maskable interrupt (R
a4eb79b... riscv: testsuite: Fix misalignment check.
85ede0d... RISC-V: Add test case for vx combine polluting VXRM
f6c89b3... RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr
70fba49... RISC-V: Rework broadcast handling [PR121073].
73c7e4e... RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.
ab58123... Change bellow in comments to below
2526631... [RISC-V] Restrict generic-vector-ooo DFA
c219fca... [RISC-V] Add missing insn types to xiangshan.md and mips-p8
c206467... RISC-V: Add test for vec_duplicate + vaaddu.vv combine for
8df4a11... RISC-V: Allow VLS DImode for sat_op vx DImode pattern
4a8c136... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
db5e2b5... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
90b8e3f... RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on G
852382a... RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and
9c965eb... RISC-V: Refine the test case for vector avg_floor and avg_c
696b8df... RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg
57921bc... [PATCH] RISC-V: Vector-scalar widening negate-multiply-(sub
3a7139d... [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro
41b4e9a... RISC-V: Support RVVDImode for avg3_ceil auto vect
bdce872... RISC-V: Fix vsetvl merge rule.
c9a9e0b... RISC-V: Refine the scalar SAT_* test cases
97e0060... RISC-V: Support RVVDImode for avg3_floor auto vect
03ee905... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
8c7dfba... RISC-V: Add testcase for rv32 SAT_MUL from uint64
d20d8c9... [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtrac
c676770... RISC-V: Add testcases for unsigned vector SAT_SUB form 11 a
d996437... RISC-V: Make zero-stride load broadcast a tunable.
8029075... [RISC-V] Detect new fusions for RISC-V
272befd... RISCV: Remove the v extension requirement for sat scalar ru
e4b1e31... RISC-V: Add test for vec_duplicate + vssub.vv combine case
e24d788... RISC-V: Add test for vec_duplicate + vssub.vv combine case
70418e1... RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2
f99e834... [PATCH] RISC-V: Enable zvfh for vector-scalar half-float ru
9c448f3... [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB
cb3bb21... [RISC-V][PR target/120642] Avoid propagating constant AVL f
3b7f156... RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
5069c34... RISC-V: Do not use vsetivli for THeadVector.
9f6ef35... RISC-V: Ignore non-types in builtin function hash.
a589511... [committed][RISC-V] Fix testsuite fallout from check-functi
dcd6be5... RISC-V: Add test cases for unsigned scalar SAT_MUL from uin
bf98bc8... RISC-V: Implement unsigned scalar SAT_MUL from uint128_t
b4e210b... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
62b1ab1... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
8ce71c4... RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2
8578937... [RISC-V] Add basic instrumentation to fusion detection
c8b1211... RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
41e6867... Refactor record_function_versions.
014cf5c... [RISC-V][PR target/118886] Refine when two insns are signal
9cd96ae... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
c49e6dc... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
18b9ffc... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
62ab97e... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
6b5d9bb... RISC-V: Reconcile the existing test due to cost model chang
7925715... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
82f59d7... RISC-V: Ignore -Oz for most rvv testcase [NFC]
7caa5ba... RISC-V: Primary vector pipeline model for sifive 7 series
dae6b21... RISC-V: Adding B ext, fp16 and missing scalar instruction t
a8109db... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
d5c0b98... RISC-V: Refactor the function bitmap_union_of_preds_with_en
b747001... RISC-V: Add pipeline-checker script
764765d... [RISC-V][PR target/119971] Avoid losing shift count masking
d0e0f72... RISC-V: update prepare_ternary_operands to handle vector-sc
ebcbac6... RISC-V: Fix build issue
8393fa2... RISC-V: Add comment and reorder the the include files in ri
11d9821... RISC-V: Add Profiles RVA/B23S64 support.
e5e953b... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
0e6b449... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
7f1849f... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
1b79fce... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
32c0f7b... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
bf7e430... RISC-V: Fix ICE for expand_select_vldi [PR120652]
e8bb1f6... [RISC-V] Force several tests to use rocket tuning
199aea6... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
6e1ce5a... RISC-V: Add test for vec_duplicate + vminu.vv combine case
4abc9d0... RISC-V: Add test for vec_duplicate + vminu.vv combine case
14e4268... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
7cd5aa1... RISC-V: Add generic tune as default.
89c1850... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
e1f983b... RISC-V: Adding cost model for zilsd
af22f68... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
5763383... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
bbd394d... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
47108b7... [PATCH v1] RISC-V: Use scratch reg for loop control
6978ac6... RISC-V: Add -fno-pie flags to testcases
ee470b5... RISC-V: Refine VX combine test case 0 to avoid code duplica
7a524c9... RISC-V: Update Profiles string in RV23.
b6eac14... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
c9a5f2b... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
db3258c... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
c3bfe3a... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
894c818... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
1f872bd... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
1b101a2... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
79b78c6... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
43de906... RISC-V: Prevent speculative vsetvl insn scheduling
f0b9a58... RISC-V: Add patterns for vector-scalar negate-(multiply-add
4d0a45b... RISC-V: testsuite: fix an obvious build error
c6f1e30... RISC-V: Regen riscv-ext.texi [NFC]
cc8b78a... RISC-V: Add test for vec_duplicate + vremu.vv combine case
c1865cd... RISC-V: Add test for vec_duplicate + vremu.vv combine case
abe3010... RISC-V: Reconcile the existing test for vremu.vx combine
cda9fc9... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
aea8e5a... [RISC-V] Enable more if-conversion on RISC-V
27eb198... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
d7b3620... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
b2d566d... RISC-V: Reconcile the existing test for vrem.vx combine
e8e0cc4... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
bad28fe... RISC-V: frm/mode-switch: robustify call_insn backtracking [
781dbef... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
b3860a2... RISC-V: frm/mode-switch: remove dubious frm edge insertion
2043b2a... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
a2ba577... [RISC-V] Handle 32bit operands in condition for conditional
928bb80... [to-be-committed][RISC-V] Handle 32bit operands in conditio
f15dbd6... RISC-V: Reconcile the existing test for vdivu.vx combine
2c37f73... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
9bd3e57... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
bf05926... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
493ff21... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
b06addf... [RISC-V] Improve signed division by 2^n
b788353... RISC-V: Don't use structured binding in riscv-common.cc
2cb6c81... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
19ada88... [RISC-V] Improve sequences to generate -1, 1 in some cases.
c558d17... RISC-V: Support Ssu64xl extension.
c21cfdd... RISC-V: Support Sstvecd extension.
ed69d9e... RISC-V: Support Sstvala extension.
f5369da... RISC-V: Support Sscounterenw extension.
babd6f0... RISC-V: Support Ssccptr extension.
532ec73... RISC-V: Support Smrnmi extension.
c88f20d... RISC-V: Support Sm/scsrind extensions.
11fec96... RISC-V: Update extension defination.
1b7f3c0... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
adf3925... [PATCH v2] RISC-V: Add svbare extension.
7914153... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
c881328... RISC-V: Add Shlcofideleg extension.
c5ad1ee... RISC-V: Reconcile the existing test for vdiv.vx combine
830cd4f... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
c8f98c3... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
131ded9... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
104ec3b... RISC-V: Use helper function to get FPR to VR move cost
d12616f... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
9a5250e... [PATCH] RISC-V: Add smcntrpmf extension.
9d95671... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
87759ca... RISC-V: Implement full-featured iterator for riscv_subset_l
ec76e0c... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
a57c75d... RISC-V: Fix line too long format issue for autovect.md [NFC
e0bab1e... RISC-V: Add test cases for avg_ceil vaadd implementation
257d3fb... RISC-V: Reconcile the existing test for avg_ceil
50331d9... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
f6633d1... RISC-V: Add minimal support of double trap extension 1.0
dd2b20b... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
cb19c72... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
87e2291... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
5ff39a6... RISC-V: Avoid division by zero in check_builtin_call [PR120
630bb2e... RISC-V: Add test cases for avg_floor vaadd implementation
5b84d31... RISC-V: Reconcile the existing test for avg_floor
1723e1e... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
1b9de35... [RISC-V] Add andi+bclr synthesis
e5a8d87... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
7792948... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
959cfe3... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
84472ea... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
c25a4a3... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
3860f7d... [RISC-V] shift+and+shift for logical and synthesis
32b10cf... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
f20ac87... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
fc3647f... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
3c2e0ef... RISC-V: Support CPUs in -march.
10350d2... RISC-V: Add autovec mode param.
b2c31a1... RISC-V: Default-initialize variable.
31805f3... RISC-V: Fix some dynamic LMUL costing.
50295e1... [RISC-V] Clear both upper and lower bits using 3 shifts
b5fb256... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
01a7d67... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
c04033b... [RISC-V] Clear high or low bits using shift pairs
4261924... [RISC-V] Improve (x << C1) + C2 split code
c2f046f... [RISC-V][PR target/120368] Fix 32bit shift on rv64
b108b7e... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
324c7fa... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
a0d9477... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
1cfdc20... [RISC-V] Infrastructure of synthesizing logical AND with co
f393f0f... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
2c0daa4... [PATCH v2 1/2] The following changes enable P8700 processor
eb95676... [RISC-V] Avoid multiple assignments to output object
001ff33... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
0468f67... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
f520787... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
a406f5d... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
f63c844... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
0c8455a... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
35eb922... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
3c80a35... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
6c6031d... [committed][RISC-V][PR target/120333] Remove bogus bext pat
db02e1f... [RISC-V] Fix false positive from Wuninitialized
0eff3cf... RISC-V: Fix the warning of temporary object dangling refere
e06e93d... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
9eead11... RISC-V: Support Zilsd code gen
30e7e3e... RISC-V: Add new operand constraint: cR
4c331a6... [RISC-V] Fix ICE due to bogus use of gen_rtvec
47c561c... [RISC-V] Avoid setting output object more than once in IOR/
f1c985c... RISC-V: Since the loop increment i++ is unreachable, the lo
ae1b1e6... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
8f135df... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
560c06a... Make end_sequence return the insn sequence
fa1c9fc... RISC-V: Reuse test name for vx combine test data [NFC]
965e1af... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
03cb5ca... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
0e65f50... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
b6d7b52... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
6784a16... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
fd9da05... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
e79595a... RISC-V: Adjust vx combine test case to avoid name conflict
2344488... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
1c7c6e2... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
0f1804c... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
65f1f1d... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
df337ed... RISC-V: Add augmented hypervisor series extensions.
dac3a0d... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
784cf1f... RISC-V: Regen riscv-ext.opt.urls
613572f... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
6a8edfa... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
2120b71... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
e06d638... RISC-V: Introduce riscv_ext_info_t to hold extension metada
6cf296c... RISC-V: Adjust riscv_can_inline_p
a430ef0... RISC-V: Generate extension table in documentation from risc
7abf721... RISC-V: Use riscv-ext.def to generate target options and va
7ac17ba... RISC-V: Introduce riscv-ext*.def to define extensions
e36df01... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
52e30b7... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
9c20668... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
98121fe... RISC-V: Support for zilsd and zclsd extensions.
198061e... testsuite: Fix RISC-V arch-52.c format issue.
3ae607e... RISC-V: Support RISC-V Profiles 23.
0e392bb... RISC-V: Support RISC-V Profiles 20/22.
24765f7... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
ad89ca4... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
f34c6e1... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
463920b... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
12f4e93... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
21b8a8d... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
6dc9157... RISC-V: Separate the test running of rvv vx_vf
c7a985b... [RISC-V][PR target/120137][PR target/120154] Don't create o
c1c086d... [PATCH] RISC-V: Minimal support for zama16b extension.
3c3f799... [RISC-V] Avoid unnecessary andi with -1 argument
7376527... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
759d682... [PATCH] RISC-V: Recognized svadu and svade extension
3049bc3... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
b486c90... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
e844422... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
329ce66... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
b427f1c... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
2a05aff... RISC-V: Add gr2vr cost helper function
8cc8438... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
a9338ad... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
29351e5... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
4888b2d... [V2][RISC-V] Trivial permutation constant derivation
339916f... [RISC-V] Adjust rvv tests after recent jump threading chang
1dcb387... [PATCH] RISC-V: Implment H modifier for printing the next r
b7a7d1f... [to-be-committed][RISC-V] Adjust testcases and finish regis
e879380... RISC-V: Remove unnecessary frm restore volatile define_insn
71d4df7... RISC-V: Allow different dynamic floating point mode to be m
73f1322... RISC-V: Fix missing implied Zicsr from Zve32x
97e8a2b... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
9d5aa2b... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
3c176c3... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
6021da7... RISC-V: Extract vector stepped for expand_const_vector [NFC
aadd08d... RISC-V: Extract vector duplicate for expand_const_vector [N
4508a2f... RISC-V: Extract vec_series for expand_const_vector [NFC]
5f8f9ad... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
2e07d3c... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
27346e9... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
70451a0... [riscv] vec_dup immediate constants in pred_broadcast expan
097eefd... [RISC-V][PR target/119865] Don't free ggc allocated memory
f9a84c7... [RISC-V][PR target/118410] Improve code generation for some
c4a9842... [RISC-V] Fix missed bext discovery
843877a... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
44f33e7... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
a0d2781... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
7ec7025... RISC-V: Use correct target in expand_vec_perm [PR121780]. (*)
05e7d54... RISC-V: Handle overlap in expand_vec_perm PR121742. (*)
0efe904... RISC-V: Always register vector built-in functions during LT (*)
6c33812... Daily bump. (*)
6ee1198... Daily bump. (*)
2cd87a7... Ada: Fix internal error on ill-formed Reduce attribute in A (*)
26f6063... Daily bump. (*)
1a8fd05... Daily bump. (*)
9bfc496... Fortran: fix assignment to allocatable scalar polymorphic c (*)
54c2398... Fortran: ICE in character(kind=4) deferred-length array ref (*)
d7709c8... Fortran: fix issues with rank-2 deferred-length character a (*)
c9be2aa... Daily bump. (*)
572ff2b... Daily bump. (*)
8ef56e1... LoongArch: Implement TARGET_CAN_INLINE_P[PR121875]. (*)
80d2ab1... Daily bump. (*)
8bc0784... match.pd: Add missing type check to reduc(ctor) pattern [PR (*)
8d99f27... c++/modules: Remove incorrect assertion [PR122015,PR122019] (*)
e67cac3... OpenMP: Unshare expr in context-selector condition [PR12192 (*)
5b1bb02... Daily bump. (*)
2360c61... libstdc++/testsuite: Unpoison 'u' on s390x in names.cc test (*)
be81c5a... c++: find_template_parameters and NTTPs [PR121981] (*)
62d6b0f... openmp: Fix up ICE in lower_omp_regimplify_operands_p [PR12 (*)
76a8b79... docs: Adjust -Wimplicit-fallthrough= documentation for C23 (*)
1f47679... testsuite: Only scan for known file extensions in lto.exp (*)
68da0af... bitint: Fix up lowering optimization of .*_OVERFLOW ifns [P (*)
761efd0... expr: Handle RAW_DATA_CST in store_constructor [PR121831] (*)
c33191a... libstdc++: Fix up <ext/pointer.h> [PR121827] (*)
1ffdfbb... testsuite, powerpc, v2: Fix vsx-vectorize-* after alignment (*)
e811195... testsuite, powerpc, v2: Fix vsx-vectorize-* after alignment (*)
cb24799... omp-expand: Initialize fd->loop.n2 if needed for the zero i (*)
931b835... c++: Fix up build_cplus_array_type [PR121524] (*)
b9e703f... tree-optimization/122016 - PRE insertion breaks abnormal co (*)
732c0a7... Deal with prior EH/abormal cleanup when fixing up noreturn (*)
6c02edc... tree-optimization/121844 - IVOPTs and asm goto in latch (*)
52438e5... tree-optimization/121659 - bogus swap of reduction operands (*)
96777e1... tree-optimization/121527 - wrong SRA with aggregate copy (*)
6348c1c... tree-optimization/121370 - avoid UB in building a CHREC (*)
e1db44e... c++/modules: Fix language linkage handling [PR122019] (*)
39daf34... Daily bump. (*)
d6ee7c1... Fortran: Use associated TBP subroutine not found [PR89092] (*)
217066a... c++: Fix canonical type for lambda pack captures [PR122015] (*)
1a04ce6... Daily bump. (*)
84ac6f3... Ada: Fix internal error on use clause present in generic fo (*)
e423467... Daily bump. (*)
e518680... Daily bump. (*)
84e2023... [MicroBlaze][PR target/118280] Fix __atomic_test_and_set (*)
8df4054... Daily bump. (*)
3e80640... Daily bump. (*)
2da8110... libstdc++: Explicitly pass -Wsystem-headers in tests that n (*)
49a8100... Remove SPR/GNR/DMR from avx512_{move,store}_by pieces tune. (*)
24c60b3... Daily bump. (*)
7da4b62... testsuite: arm: Simplify fp16-aapcs tests (*)
b2c626e... Daily bump. (*)
ae981f4... Fix latent LRA bug (*)
a584cd7... aarch64: Force vector in SVE gimple_folder::fold_active_lan (*)
9373c48... arm: Fix operand check for __arm_{mrrc{2},mcrr{2]} intrinsi (*)
516e479... Daily bump. (*)
a04c1e9... ada: Fix internal error on aspect in complex object declara (*)
3846068... ada: Fix wrong finalization of aliased array of bounded vec (*)
6e1f5f7... ada: Fix crash on iterator of type with Constant_Indexing a (*)
150859c... aarch64: PR target/121749: Use dg-assemble in testcase (*)
b8c702f... aarch64: PR target/121749: Use correct predicate for narrow (*)
f0767ec... AVR: Support AVR32EB14/20/28/32. (*)
4dd2885... LoongArch: Fix wrong code from bstrpick split (*)
1649319... c++: Fix mangling of _Float16 template args [PR121801] (*)
866464a... Daily bump. (*)
3c0b35c... Daily bump. (*)
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