https://gcc.gnu.org/g:08161d0c1948d98660c5c030f314a653857318cc
commit 08161d0c1948d98660c5c030f314a653857318cc Author: Pan Li <[email protected]> Date: Thu May 8 11:21:35 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 1 Add asm dump check and for vec_duplicate + vadd.vv combine case 1 to vadd.vx with the cost of GR2VR is 1. The testcases is not that tidy according to the result, but we will continue tuning the cost model for this. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c: New test. Signed-off-by: Pan Li <[email protected]> (cherry picked from commit 6a718d401d37880a5ed74210b1a75783e8ea9c38) Diff: --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c | 8 ++++++++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c | 8 ++++++++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c | 8 ++++++++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c | 8 ++++++++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c | 8 ++++++++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c | 8 ++++++++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c | 8 ++++++++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c | 8 ++++++++ 8 files changed, 64 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c new file mode 100644 index 000000000000..e5ec8884fc71 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int16_t, +, VX_BINARY_BODY_X8) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c new file mode 100644 index 000000000000..ed6c22d059f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int32_t, +, VX_BINARY_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c new file mode 100644 index 000000000000..ef44012e418f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int64_t, +, VX_BINARY_BODY) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c new file mode 100644 index 000000000000..d61f9dfbb2b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int8_t, +, VX_BINARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c new file mode 100644 index 000000000000..3d1ba7f07422 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint16_t, +, VX_BINARY_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c new file mode 100644 index 000000000000..2e9862be6b22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint32_t, +, VX_BINARY_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c new file mode 100644 index 000000000000..72e6786a0a5c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint64_t, +, VX_BINARY_BODY) + +/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c new file mode 100644 index 000000000000..e935be1552c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint8_t, +, VX_BINARY_BODY_X16) + +/* { dg-final { scan-assembler {vadd.vx} } } */
