https://gcc.gnu.org/g:b86b8dc70d54702694917ede31221402ed8ccff3
commit b86b8dc70d54702694917ede31221402ed8ccff3 Author: Alexey Merzlyakov <[email protected]> Date: Wed Jul 2 11:29:00 2025 -0600 [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356] It corrects the shift type of interleaved stepped patterns for const vector expanding in LRA. The shift instruction was initially LSHIFTRT, and it seems still should be the same type for both LRA and other cases. PR target/120356 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector_interleaved_stepped_npatterns): Fix ASHIFT to LSHIFTRT insn. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr120356.c: New test. (cherry picked from commit 9c1ed63e4c6b0f80dd47ce421dd7d80d52c38fd3) Diff: --- gcc/config/riscv/riscv-v.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 69f2a1ece534..ce1633c72dee 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1598,7 +1598,7 @@ expand_const_vector_interleaved_stepped_npatterns (rtx target, rtx src, shifted_vid = gen_reg_rtx (mode); rtx shift = gen_int_mode (1, Xmode); rtx shift_ops[] = {shifted_vid, vid, shift}; - emit_vlmax_insn (code_for_pred_scalar (ASHIFT, mode), BINARY_OP, + emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, mode), BINARY_OP, shift_ops); } else
