https://gcc.gnu.org/g:5ab026d389d5bf4b754e7e028dec1358b6cfa547
commit 5ab026d389d5bf4b754e7e028dec1358b6cfa547
Author: GCC Administrator <gccad...@gcc.gnu.org>
Date: Sun Jul 20 00:17:36 2025 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 34 ++++++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/testsuite/ChangeLog | 22 ++++++++++++++++++++++
3 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a75b0c8052bd..12b0d90c48aa 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,37 @@
+2025-07-19 Dimitar Dimitrov <dimi...@dinux.eu>
+
+ PR target/121124
+ * config/pru/pru-pragma.cc (pru_pragma_ctable_entry): Handle the
+ ctable base address as signed 32-bit value, and sign-extend to
+ HOST_WIDE_INT.
+ * config/pru/pru-protos.h (struct pru_ctable_entry): Store the
+ ctable base address as signed.
+ (pru_get_ctable_exact_base_index): Pass base address as signed.
+ (pru_get_ctable_base_index): Ditto.
+ (pru_get_ctable_base_offset): Ditto.
+ * config/pru/pru.cc (pru_get_ctable_exact_base_index): Ditto.
+ (pru_get_ctable_base_index): Ditto.
+ (pru_get_ctable_base_offset): Ditto.
+ (pru_print_operand_address): Ditto.
+
+2025-07-19 Paul-Antoine Arras <par...@baylibre.com>
+
+ PR target/119100
+ * config/riscv/autovec-opt.md (*vfwnmacc_vf_<mode>): New pattern.
+ (*vfwnmsac_vf_<mode>): New pattern.
+ * config/riscv/riscv.cc (get_vector_binary_rtx_cost): Add support for a
+ vec_duplicate in a neg.
+
+2025-07-19 Artemiy Volkov <artem...@acm.org>
+
+ * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Protect
+ from a NULL PREV_SET or CURR_SET.
+
+2025-07-19 Georg-Johann Lay <a...@gjlay.de>
+
+ * config/avr/avr-passes.cc (avr_optimize_casesi): Fuse
+ get_insns() with end_sequence().
+
2025-07-18 Pan Li <pan2...@intel.com>
* config/riscv/autovec.md (avg<mode>3_ceil): Add new pattern
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index c64e4865ca87..eafd44957d21 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250719
+20250720
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ad467e69abe0..affea6525191 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,25 @@
+2025-07-19 Dimitar Dimitrov <dimi...@dinux.eu>
+
+ PR target/121124
+ * gcc.target/pru/pragma-ctable_entry-2.c: New test.
+
+2025-07-19 Paul-Antoine Arras <par...@baylibre.com>
+
+ PR target/119100
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfwnmacc and
+ vfwnmsac.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f32.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f32.c: New test.
+
2025-07-18 Harald Anlauf <anl...@gmx.de>
PR fortran/121145
