https://gcc.gnu.org/g:71bee51da51e6cd1ce25dd48c69c2aaf8840791b
commit 71bee51da51e6cd1ce25dd48c69c2aaf8840791b
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Tue Jun 10 18:07:26 2025 -0400
PR target/117251: Add PowerPC XXEVAL support to speed up SHA3 calculations
2025-06-10 Michael Meissner <meiss...@linux.ibm.com>
gcc/
PR target/117251
* config/rs6000/fusion.md: Regenerate.
* config/rs6000/genfusion.pl (gen_logical_addsubf): Add support to
generate vector nor => nand fusion if XXEVAL is supported.
Diff:
---
gcc/config/rs6000/fusion.md | 15 +++++++++------
gcc/config/rs6000/genfusion.pl | 1 +
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index c1be0e5ff8f1..01b7fda17ecc 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -2414,20 +2414,23 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vnand
(define_insn "*fuse_vnor_vnand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
- (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v"))))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v")
+ (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,wa,v"))
+ (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,wa,v"))))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,wa,v"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))]
"(TARGET_P10_FUSION)"
"@
vnor %3,%1,%0\;vnand %3,%3,%2
vnor %3,%1,%0\;vnand %3,%3,%2
vnor %3,%1,%0\;vnand %3,%3,%2
+ xxeval %x3,%x2,%x1,%x0,247
vnor %4,%1,%0\;vnand %3,%4,%2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,yes,*")
+ (set_attr "isa" "*,*,*,xxeval,*")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vnand
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 4c70237d2d27..d4965b6df864 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -254,6 +254,7 @@ sub gen_logical_addsubf
"vnand_vnand" => 241,
"vorc_vnand" => 244,
"veqv_vnand" => 246,
+ "vnor_vnand" => 247,
);
KIND: foreach $kind ('scalar','vector') {
