https://gcc.gnu.org/g:da4c90c90663de48e981b697aabdd84b69e5fcc2
commit da4c90c90663de48e981b697aabdd84b69e5fcc2
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Fri Nov 15 22:44:54 2024 -0500
Change TARGET_CMPB to TARGET_POWER6.
This patch changes TARGET_CMPB to TARGET_POWER6. The -mcmpb switch is not
being
changed, just the name of the macros used to determine if the PowerPC
processor
supports ISA 2.5 (Power6).
2024-11-15 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_CMPB to TARGET_POWER6.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_emit_parity): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_LFIWAX): Likewise.
(TARGET_POWER6): New macro.
(TARGET_EXTRA_BUILTINS): Change TARGET_CMPB to TARGET_POWER6.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(parity<mode>2_cmp): Likewise.
(cmpb<mode>3): Likewise.
(copysign<mode>3): Likewise.
(copysign<mode>3_fcpsgn): Likewise.
(cmpstrnsi): Likewise.
(cmpstrsi): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
gcc/config/rs6000/rs6000.cc | 8 ++++----
gcc/config/rs6000/rs6000.h | 7 ++++---
gcc/config/rs6000/rs6000.md | 16 ++++++++--------
4 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 98a0545030cd..76421bd1de0b 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_P5:
return TARGET_POWER5;
case ENB_P6:
- return TARGET_CMPB;
+ return TARGET_POWER6;
case ENB_P6_64:
- return TARGET_CMPB && TARGET_POWERPC64;
+ return TARGET_POWER6 && TARGET_POWERPC64;
case ENB_P7:
return TARGET_POPCNTD;
case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 8dfaea5df070..ca5d66beb37e 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3920,7 +3920,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
else if (TARGET_DFP)
rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
- else if (TARGET_CMPB)
+ else if (TARGET_POWER6)
rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
else if (TARGET_POWER5X)
rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
@@ -4796,7 +4796,7 @@ rs6000_option_override_internal (bool global_init_p)
DERAT mispredict penalty. However the LVE and STVE altivec instructions
need indexed accesses and the type used is the scalar type of the element
being loaded or stored. */
- TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
+ TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_POWER6
&& !TARGET_ALTIVEC);
/* Set the -mrecip options. */
@@ -22435,7 +22435,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int
outer_code,
return false;
case PARITY:
- *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
+ *total = COSTS_N_INSNS (TARGET_POWER6 ? 2 : 6);
return false;
case NOT:
@@ -23262,7 +23262,7 @@ rs6000_emit_parity (rtx dst, rtx src)
tmp = gen_reg_rtx (mode);
/* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
- if (TARGET_CMPB)
+ if (TARGET_POWER6)
{
if (mode == SImode)
{
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 8573b8594052..1b10802a87f4 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -449,12 +449,12 @@ extern int rs6000_vector_align[];
#define TARGET_FCFID (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_POWER5 /* ISA 2.02 */ \
- || TARGET_CMPB /* ISA 2.05 */ \
+ || TARGET_POWER6 /* ISA 2.05 */ \
|| TARGET_POPCNTD) /* ISA 2.06 */
#define TARGET_FCTIDZ TARGET_FCFID
#define TARGET_STFIWX TARGET_PPC_GFXOPT
-#define TARGET_LFIWAX TARGET_CMPB
+#define TARGET_LFIWAX TARGET_POWER6
#define TARGET_LFIWZX TARGET_POPCNTD
#define TARGET_FCFIDS TARGET_POPCNTD
#define TARGET_FCFIDU TARGET_POPCNTD
@@ -504,6 +504,7 @@ extern int rs6000_vector_align[];
/* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */
#define TARGET_POWER5 TARGET_POPCNTB
#define TARGET_POWER5X TARGET_FPRND
+#define TARGET_POWER6 TARGET_CMPB
/* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. The MASK_<xxxx>
@@ -532,7 +533,7 @@ extern int rs6000_vector_align[];
#define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_POWER5 /* ISA 2.02 */ \
- || TARGET_CMPB /* ISA 2.05 */ \
+ || TARGET_POWER6 /* ISA 2.05 */ \
|| TARGET_POPCNTD /* ISA 2.06 */ \
|| TARGET_ALTIVEC \
|| TARGET_VSX \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index e7c532fbaa07..07eae9ca0c55 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -383,7 +383,7 @@
(const_int 1)
(and (eq_attr "isa" "p6")
- (match_test "TARGET_CMPB"))
+ (match_test "TARGET_POWER6"))
(const_int 1)
(and (eq_attr "isa" "p7")
@@ -2544,7 +2544,7 @@
(define_insn "parity<mode>2_cmpb"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
UNSPEC_PARITY))]
- "TARGET_CMPB && TARGET_POPCNTB"
+ "TARGET_POWER6 && TARGET_POPCNTB"
"prty<wd> %0,%1"
[(set_attr "type" "popcnt")])
@@ -2597,7 +2597,7 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "gpc_reg_operand" "r")] UNSPEC_CMPB))]
- "TARGET_CMPB"
+ "TARGET_POWER6"
"cmpb %0,%1,%2"
[(set_attr "type" "cmp")])
@@ -5401,7 +5401,7 @@
&& ((TARGET_PPC_GFXOPT
&& !HONOR_NANS (<MODE>mode)
&& !HONOR_SIGNED_ZEROS (<MODE>mode))
- || TARGET_CMPB
+ || TARGET_POWER6
|| VECTOR_UNIT_VSX_P (<MODE>mode))"
{
/* Middle-end canonicalizes -fabs (x) to copysign (x, -1),
@@ -5422,7 +5422,7 @@
if (!gpc_reg_operand (operands[2], <MODE>mode))
operands[2] = copy_to_mode_reg (<MODE>mode, operands[2]);
- if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
+ if (TARGET_POWER6 || VECTOR_UNIT_VSX_P (<MODE>mode))
{
emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
operands[2]));
@@ -5438,7 +5438,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(copysign:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
(match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
- "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))"
+ "TARGET_HARD_FLOAT && (TARGET_POWER6 || VECTOR_UNIT_VSX_P (<MODE>mode))"
"@
fcpsgn %0,%2,%1
xscpsgndp %x0,%x2,%x1"
@@ -10122,7 +10122,7 @@
(match_operand:BLK 2)))
(use (match_operand:SI 3))
(use (match_operand:SI 4))])]
- "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
+ "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
{
if (optimize_insn_for_size_p ())
FAIL;
@@ -10144,7 +10144,7 @@
(compare:SI (match_operand:BLK 1)
(match_operand:BLK 2)))
(use (match_operand:SI 3))])]
- "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
+ "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
{
if (optimize_insn_for_size_p ())
FAIL;
