https://gcc.gnu.org/g:ea3294aa02e54f46a37083805e9f83b4e55ab7b6
commit ea3294aa02e54f46a37083805e9f83b4e55ab7b6
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Thu Nov 14 18:10:51 2024 -0500
Change TARGET_CMPB to TARGET_POWER6.
This patch changes TARGET_CMPB to TARGET_POWER6 and OPTION_MASK_CMPB to
OPTION_MASK_POWER6. The -mcmpb switch is not being changed, just the name
of
the macros used to determine if the PowerPC processor supports ISA 2.5
(Power6).
2024-11-14 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_CMPB to TARGET_POWER6. Change OPTION_MASK_CMPB to
OPTION_MASK_POWER6.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros):
Likewise.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED):
Likewise.
(POWERPC_MASKS): Likewise.
(476 cpu definition): Likewise.
(476fp cpu definition): Likewise.
(a2 cpu definition): Likewise.
(power6 cpu definition): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_clone_map): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_emit_parity): Likewise.
(rs6000_opt_masks): Likewise.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_LFIWAX): Likewise.
(TARGET_EXTRA_BUILTINS): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(parity<mode>2_cmp): Change TARGET_CMPB to TARGET_POWER6. Change
OPTION_MASK_CMPB to OPTION_MASK_POWER6. Eliminate redundant
TARGET_POWER5 test.
(cmpb<mode>3): Change TARGET_CMPB to TARGET_POWER6. Change
OPTION_MASK_CMPB to OPTION_MASK_POWER6.
(copysign<mode>3): Likewise.
(copysign<mode>3_fcpsgn): Likewise.
(cmpstrnsi): Likewise.
(cmpstrsi): Likewise.
* gcc/config/rs6000/rs6000.opt (-mcmpb): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
gcc/config/rs6000/rs6000-c.cc | 2 +-
gcc/config/rs6000/rs6000-cpus.def | 14 +++++++-------
gcc/config/rs6000/rs6000.cc | 12 ++++++------
gcc/config/rs6000/rs6000.h | 6 +++---
gcc/config/rs6000/rs6000.md | 16 ++++++++--------
gcc/config/rs6000/rs6000.opt | 8 +++++---
7 files changed, 32 insertions(+), 30 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 98a0545030cd..76421bd1de0b 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_P5:
return TARGET_POWER5;
case ENB_P6:
- return TARGET_CMPB;
+ return TARGET_POWER6;
case ENB_P6_64:
- return TARGET_CMPB && TARGET_POWERPC64;
+ return TARGET_POWER6 && TARGET_POWERPC64;
case ENB_P7:
return TARGET_POPCNTD;
case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index c9ef36b77639..b721c9925e19 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -426,7 +426,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
if ((flags & OPTION_MASK_POWER5X) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
- if ((flags & OPTION_MASK_CMPB) != 0)
+ if ((flags & OPTION_MASK_POWER6) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
if ((flags & OPTION_MASK_POPCNTD) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index b347053576db..77cc199073e3 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -28,7 +28,7 @@
power6. In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
as optional. Group masks by server and embedded. */
#define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \
- | OPTION_MASK_CMPB \
+ | OPTION_MASK_POWER6 \
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_PPC_GFXOPT \
| OPTION_MASK_PPC_GPOPT)
@@ -117,7 +117,7 @@
/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
- | OPTION_MASK_CMPB \
+ | OPTION_MASK_POWER6 \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DFP \
| OPTION_MASK_DLMZB \
@@ -185,11 +185,11 @@ RS6000_CPU ("464", PROCESSOR_PPC440,
OPTION_MASK_SOFT_FLOAT
RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("476", PROCESSOR_PPC476, OPTION_MASK_SOFT_FLOAT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
- | OPTION_MASK_POWER5X | OPTION_MASK_CMPB | OPTION_MASK_MULHW
+ | OPTION_MASK_POWER5X | OPTION_MASK_POWER6 | OPTION_MASK_MULHW
| OPTION_MASK_DLMZB)
RS6000_CPU ("476fp", PROCESSOR_PPC476, OPTION_MASK_PPC_GFXOPT
| OPTION_MASK_MFCRF | OPTION_MASK_POWER5 | OPTION_MASK_POWER5X
- | OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
+ | OPTION_MASK_POWER6 | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE)
RS6000_CPU ("602", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT)
@@ -209,7 +209,7 @@ RS6000_CPU ("823", PROCESSOR_MPCCORE,
OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | OPTION_MASK_ISEL)
RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | OPTION_MASK_ISEL)
RS6000_CPU ("a2", PROCESSOR_PPCA2, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64
- | OPTION_MASK_POWER5 | OPTION_MASK_CMPB
+ | OPTION_MASK_POWER5 | OPTION_MASK_POWER6
| OPTION_MASK_NO_UPDATE)
RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
@@ -242,11 +242,11 @@ RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 |
OPTION_MASK_PPC_GPOPT
| OPTION_MASK_POWER5X)
RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
- | OPTION_MASK_POWER5X | OPTION_MASK_CMPB | OPTION_MASK_DFP
+ | OPTION_MASK_POWER5X | OPTION_MASK_POWER6 | OPTION_MASK_DFP
| OPTION_MASK_RECIP_PRECISION)
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
- | OPTION_MASK_POWER5X | OPTION_MASK_CMPB | OPTION_MASK_DFP
+ | OPTION_MASK_POWER5X | OPTION_MASK_POWER6 | OPTION_MASK_DFP
| OPTION_MASK_RECIP_PRECISION)
RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 4a2d0250956e..36129248299c 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -258,7 +258,7 @@ struct clone_map {
static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
{ 0, "" }, /* Default options. */
- { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
+ { OPTION_MASK_POWER6, "arch_2_05" }, /* ISA 2.05 (power6).
*/
{ OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
{ OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
{ OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.0 (power9). */
@@ -3920,7 +3920,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
else if (TARGET_DFP)
rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
- else if (TARGET_CMPB)
+ else if (TARGET_POWER6)
rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
else if (TARGET_POWER5X)
rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
@@ -4796,7 +4796,7 @@ rs6000_option_override_internal (bool global_init_p)
DERAT mispredict penalty. However the LVE and STVE altivec instructions
need indexed accesses and the type used is the scalar type of the element
being loaded or stored. */
- TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
+ TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_POWER6
&& !TARGET_ALTIVEC);
/* Set the -mrecip options. */
@@ -22435,7 +22435,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int
outer_code,
return false;
case PARITY:
- *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
+ *total = COSTS_N_INSNS (TARGET_POWER6 ? 2 : 6);
return false;
case NOT:
@@ -23262,7 +23262,7 @@ rs6000_emit_parity (rtx dst, rtx src)
tmp = gen_reg_rtx (mode);
/* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
- if (TARGET_CMPB)
+ if (TARGET_POWER6)
{
if (mode == SImode)
{
@@ -24482,7 +24482,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
false, true },
{ "block-ops-vector-pair", OPTION_MASK_BLOCK_OPS_VECTOR_PAIR,
false, true },
- { "cmpb", OPTION_MASK_CMPB, false, true },
+ { "cmpb", OPTION_MASK_POWER6, false, true },
{ "crypto", OPTION_MASK_CRYPTO, false, true },
{ "direct-move", 0, false, true },
{ "dlmzb", OPTION_MASK_DLMZB, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 645f9b33d866..5b4cb9500a06 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -449,12 +449,12 @@ extern int rs6000_vector_align[];
#define TARGET_FCFID (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_POWER5 /* ISA 2.02 */ \
- || TARGET_CMPB /* ISA 2.05 */ \
+ || TARGET_POWER6 /* ISA 2.05 */ \
|| TARGET_POPCNTD) /* ISA 2.06 */
#define TARGET_FCTIDZ TARGET_FCFID
#define TARGET_STFIWX TARGET_PPC_GFXOPT
-#define TARGET_LFIWAX TARGET_CMPB
+#define TARGET_LFIWAX TARGET_POWER6
#define TARGET_LFIWZX TARGET_POPCNTD
#define TARGET_FCFIDS TARGET_POPCNTD
#define TARGET_FCFIDU TARGET_POPCNTD
@@ -528,7 +528,7 @@ extern int rs6000_vector_align[];
#define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_POWER5 /* ISA 2.02 */ \
- || TARGET_CMPB /* ISA 2.05 */ \
+ || TARGET_POWER6 /* ISA 2.05 */ \
|| TARGET_POPCNTD /* ISA 2.06 */ \
|| TARGET_ALTIVEC \
|| TARGET_VSX \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1ad2d46a1fbf..53c175e161e1 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -383,7 +383,7 @@
(const_int 1)
(and (eq_attr "isa" "p6")
- (match_test "TARGET_CMPB"))
+ (match_test "TARGET_POWER6"))
(const_int 1)
(and (eq_attr "isa" "p7")
@@ -2544,7 +2544,7 @@
(define_insn "parity<mode>2_cmpb"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
UNSPEC_PARITY))]
- "TARGET_CMPB && TARGET_POWER5"
+ "TARGET_POWER6"
"prty<wd> %0,%1"
[(set_attr "type" "popcnt")])
@@ -2597,7 +2597,7 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "gpc_reg_operand" "r")] UNSPEC_CMPB))]
- "TARGET_CMPB"
+ "TARGET_POWER6"
"cmpb %0,%1,%2"
[(set_attr "type" "cmp")])
@@ -5401,7 +5401,7 @@
&& ((TARGET_PPC_GFXOPT
&& !HONOR_NANS (<MODE>mode)
&& !HONOR_SIGNED_ZEROS (<MODE>mode))
- || TARGET_CMPB
+ || TARGET_POWER6
|| VECTOR_UNIT_VSX_P (<MODE>mode))"
{
/* Middle-end canonicalizes -fabs (x) to copysign (x, -1),
@@ -5422,7 +5422,7 @@
if (!gpc_reg_operand (operands[2], <MODE>mode))
operands[2] = copy_to_mode_reg (<MODE>mode, operands[2]);
- if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
+ if (TARGET_POWER6 || VECTOR_UNIT_VSX_P (<MODE>mode))
{
emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
operands[2]));
@@ -5438,7 +5438,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(copysign:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
(match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
- "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))"
+ "TARGET_HARD_FLOAT && (TARGET_POWER6 || VECTOR_UNIT_VSX_P (<MODE>mode))"
"@
fcpsgn %0,%2,%1
xscpsgndp %x0,%x2,%x1"
@@ -10122,7 +10122,7 @@
(match_operand:BLK 2)))
(use (match_operand:SI 3))
(use (match_operand:SI 4))])]
- "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
+ "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
{
if (optimize_insn_for_size_p ())
FAIL;
@@ -10144,7 +10144,7 @@
(compare:SI (match_operand:BLK 1)
(match_operand:BLK 2)))
(use (match_operand:SI 3))])]
- "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
+ "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
{
if (optimize_insn_for_size_p ())
FAIL;
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 797fd9a77d76..5e040d84526e 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -138,11 +138,13 @@ Use ISA 2.2 (Power5) instructions.
;; but change the target macro.
mfprnd
Target Mask(POWER5X) Var(rs6000_isa_flags)
-Use ISA 2.4 (Power5x) instructions.
+Use ISA 2.2 (Power5x) instructions.
+;; Originally, we used -mcmpb to indicate ISA 2.5. Keep the switch name,
+;; but change the target macro.
mcmpb
-Target Mask(CMPB) Var(rs6000_isa_flags)
-Use PowerPC V2.05 compare bytes instruction.
+Target Mask(POWER6) Var(rs6000_isa_flags)
+Use ISA 2.5 (Power6) instructions.
;; This option existed in the past, but now is always off.
mno-mfpgpr
