https://gcc.gnu.org/g:f02415dc2edcd7777ea220c4b7bd8af8a8ad7b0f
commit f02415dc2edcd7777ea220c4b7bd8af8a8ad7b0f
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Thu Nov 14 12:52:59 2024 -0500
Change TARGET_POPCNTB to TARGET_POWER5.
This patch changes TARGET_POPCNTB to TARGET_POWER5 and OPTION_MASK_POPCNTB
to
OPTION_MASK_POWER5. The -mpopcntb switch is not being changed, just the
name of
the macros used to determine if the PowerPC processor supports ISA 2.2
(Power5).
2024-11-14 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Change TARGET_POPCNTB to TARGET_POWER5. Change OPTION_MASK_POPCNTB
to
OPTION_MASK_POWER5.
* gcc/config/rs6000/rs6000-c.cc (rs6000_target_modify_macros):
Likewise.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_2_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
(476 cpu definition): Likewise.
(476fp cpu definition): Likewise.
(a2 cpu definition): Likewise.
(power5 cpu definition): Likewise.
(power5+ cpu definition): Likewise.
(power6 cpu definition): Likewise.
(power6x cpu definition): Likewise.
* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_emit_popcount): Update comment.
(rs6000_emit_parity): Likewise.
(rs6000_opt_masks): Change TARGET_POPCNTB to TARGET_POWER5. Change
OPTION_MASK_POPCNTB to OPTION_MASK_POWER5.
* gcc/config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_EXTRA_BUILTINS): Likewise.
(TARGET_FRE): Likewise.
(TARGET_FRSQRTES): Likewise.
* gcc/config/rs6000/rs6000.md (enabled attribute): Likewise.
(popcount<mode>2): Likewise.
(popcntb<mode>): Likewise.
(popcntd<mode>): Likewise.
(parity<mode>2): Likewise.
* gcc/config/rs6000/rs6000.md (-mpopcntb): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 2 +-
gcc/config/rs6000/rs6000-c.cc | 2 +-
gcc/config/rs6000/rs6000-cpus.def | 18 +++++++++---------
gcc/config/rs6000/rs6000.cc | 10 +++++-----
gcc/config/rs6000/rs6000.h | 8 ++++----
gcc/config/rs6000/rs6000.md | 12 ++++++------
gcc/config/rs6000/rs6000.opt | 6 ++++--
7 files changed, 30 insertions(+), 28 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 9bdbae1ecf94..98a0545030cd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_ALWAYS:
return true;
case ENB_P5:
- return TARGET_POPCNTB;
+ return TARGET_POWER5;
case ENB_P6:
return TARGET_CMPB;
case ENB_P6_64:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 4dc80e598fa4..da3a9c2d8406 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -422,7 +422,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
if ((flags & OPTION_MASK_MFCRF) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
- if ((flags & OPTION_MASK_POPCNTB) != 0)
+ if ((flags & OPTION_MASK_POWER5) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
if ((flags & OPTION_MASK_FPRND) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 84fac8bdac1d..d600f123d6a7 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -21,7 +21,7 @@
/* ISA masks. */
#ifndef ISA_2_1_MASKS
#define ISA_2_1_MASKS OPTION_MASK_MFCRF
-#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
+#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POWER5)
#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND)
/* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
@@ -143,7 +143,7 @@
| OPTION_MASK_P9_VECTOR \
| OPTION_MASK_PCREL \
| OPTION_MASK_PCREL_OPT \
- | OPTION_MASK_POPCNTB \
+ | OPTION_MASK_POWER5 \
| OPTION_MASK_POPCNTD \
| OPTION_MASK_POWERPC64 \
| OPTION_MASK_PPC_GFXOPT \
@@ -184,11 +184,11 @@ RS6000_CPU ("464", PROCESSOR_PPC440,
OPTION_MASK_SOFT_FLOAT
| OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("476", PROCESSOR_PPC476, OPTION_MASK_SOFT_FLOAT
- | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
+ | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
| OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_MULHW
| OPTION_MASK_DLMZB)
RS6000_CPU ("476fp", PROCESSOR_PPC476, OPTION_MASK_PPC_GFXOPT
- | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND
+ | OPTION_MASK_MFCRF | OPTION_MASK_POWER5 | OPTION_MASK_FPRND
| OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE)
@@ -209,7 +209,7 @@ RS6000_CPU ("823", PROCESSOR_MPCCORE,
OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | OPTION_MASK_ISEL)
RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | OPTION_MASK_ISEL)
RS6000_CPU ("a2", PROCESSOR_PPCA2, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64
- | OPTION_MASK_POPCNTB | OPTION_MASK_CMPB
+ | OPTION_MASK_POWER5 | OPTION_MASK_CMPB
| OPTION_MASK_NO_UPDATE)
RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
@@ -236,16 +236,16 @@ RS6000_CPU ("power3", PROCESSOR_PPC630,
OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF)
RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
- | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB)
+ | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5)
RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
- | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
+ | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
| OPTION_MASK_FPRND)
RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
- | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
+ | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
| OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP
| OPTION_MASK_RECIP_PRECISION)
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
- | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
+ | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
| OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP
| OPTION_MASK_RECIP_PRECISION)
RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 950fd947fda3..786c6a34fc70 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3924,7 +3924,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
else if (TARGET_FPRND)
rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
- else if (TARGET_POPCNTB)
+ else if (TARGET_POWER5)
rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
else if (TARGET_ALTIVEC)
rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
@@ -23208,8 +23208,8 @@ rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
return;
}
-/* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
- (Power7) targets. DST is the target, and SRC is the argument operand. */
+/* Emit popcount intrinsic on TARGET_POWER5 and TARGET_POPCNTD (Power7)
+ targets. DST is the target, and SRC is the argument operand. */
void
rs6000_emit_popcount (rtx dst, rtx src)
@@ -23250,7 +23250,7 @@ rs6000_emit_popcount (rtx dst, rtx src)
}
-/* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
+/* Emit parity intrinsic on TARGET_POWER5 targets. DST is the
target, and SRC is the argument operand. */
void
@@ -24504,7 +24504,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "multiple", OPTION_MASK_MULTIPLE, false,
true },
{ "pcrel", OPTION_MASK_PCREL, false, true },
{ "pcrel-opt", OPTION_MASK_PCREL_OPT, false, true },
- { "popcntb", OPTION_MASK_POPCNTB, false, true },
+ { "power5", OPTION_MASK_POWER5, false, true },
{ "popcntd", OPTION_MASK_POPCNTD, false, true },
{ "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
{ "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index d460eb065448..645f9b33d866 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -448,7 +448,7 @@ extern int rs6000_vector_align[];
Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
#define TARGET_FCFID (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
- || TARGET_POPCNTB /* ISA 2.02 */ \
+ || TARGET_POWER5 /* ISA 2.02 */ \
|| TARGET_CMPB /* ISA 2.05 */ \
|| TARGET_POPCNTD) /* ISA 2.06 */
@@ -527,7 +527,7 @@ extern int rs6000_vector_align[];
#define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
- || TARGET_POPCNTB /* ISA 2.02 */ \
+ || TARGET_POWER5 /* ISA 2.02 */ \
|| TARGET_CMPB /* ISA 2.05 */ \
|| TARGET_POPCNTD /* ISA 2.06 */ \
|| TARGET_ALTIVEC \
@@ -543,9 +543,9 @@ extern int rs6000_vector_align[];
#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
#define TARGET_FRE (TARGET_HARD_FLOAT \
- && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
+ && (TARGET_POWER5 || VECTOR_UNIT_VSX_P (DFmode)))
-#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
+#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POWER5 \
&& TARGET_PPC_GFXOPT)
#define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 8eda2f7bb0d7..2b64047047ef 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -379,7 +379,7 @@
(const_int 1)
(and (eq_attr "isa" "p5")
- (match_test "TARGET_POPCNTB"))
+ (match_test "TARGET_POWER5"))
(const_int 1)
(and (eq_attr "isa" "p6")
@@ -2510,7 +2510,7 @@
(define_expand "popcount<mode>2"
[(set (match_operand:GPR 0 "gpc_reg_operand")
(popcount:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
- "TARGET_POPCNTB || TARGET_POPCNTD"
+ "TARGET_POWER5 || TARGET_POPCNTD"
{
rs6000_emit_popcount (operands[0], operands[1]);
DONE;
@@ -2520,8 +2520,8 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
UNSPEC_POPCNTB))]
- "TARGET_POPCNTB"
- "popcntb %0,%1"
+ "TARGET_POWER5"
+ "power5 %0,%1"
[(set_attr "type" "popcnt")])
(define_insn "popcntd<mode>2"
@@ -2535,7 +2535,7 @@
(define_expand "parity<mode>2"
[(set (match_operand:GPR 0 "gpc_reg_operand")
(parity:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
- "TARGET_POPCNTB"
+ "TARGET_POWER5"
{
rs6000_emit_parity (operands[0], operands[1]);
DONE;
@@ -2544,7 +2544,7 @@
(define_insn "parity<mode>2_cmpb"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
UNSPEC_PARITY))]
- "TARGET_CMPB && TARGET_POPCNTB"
+ "TARGET_CMPB && TARGET_POWER5"
"prty<wd> %0,%1"
[(set_attr "type" "popcnt")])
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 94323bd1db26..24f2af208856 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -128,9 +128,11 @@ mmfcrf
Target Mask(MFCRF) Var(rs6000_isa_flags)
Use PowerPC V2.01 single field mfcr instruction.
+;; Originally, we used -mpopcntb to indicate ISA 2.2. Keep the switch name,
+;; but change the target macro.
mpopcntb
-Target Mask(POPCNTB) Var(rs6000_isa_flags)
-Use PowerPC V2.02 popcntb instruction.
+Target Mask(POWER5) Var(rs6000_isa_flags)
+Use ISA 2.2 (Power5) instructions.
mfprnd
Target Mask(FPRND) Var(rs6000_isa_flags)
