https://gcc.gnu.org/g:8b1146fe46e62f8b03bd9ddee48995794e192e82
commit r14-10824-g8b1146fe46e62f8b03bd9ddee48995794e192e82
Author: Torbjörn SVENSSON <torbjorn.svens...@foss.st.com>
Date: Sun Oct 20 11:48:42 2024 +0200
testsuite: arm: Use check-function-bodies in fp16-aapcs-* tests
Converted the tests to use check-function-bodies in order to ensure that
the sequence is correct.
gcc/testsuite/ChangeLog:
* gcc.target/arm/fp16-aapcs-1.c: Use check-function-bodies.
* gcc.target/arm/fp16-aapcs-2.c: Likewise.
* gcc.target/arm/fp16-aapcs-3.c: Likewise.
* gcc.target/arm/fp16-aapcs-4.c: Likewise.
Signed-off-by: Torbjörn SVENSSON <torbjorn.svens...@foss.st.com>
(cherry picked from commit 205515da82a2914d765e74ba73fd2765e1254112)
Diff:
---
gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c | 53 +++++++++++++++++++++++++---
gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c | 31 ++++++++++++++---
gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c | 54 +++++++++++++++++++++++++----
gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c | 31 ++++++++++++++---
4 files changed, 150 insertions(+), 19 deletions(-)
diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c
b/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c
index 0a0a60f35033..b18d7cda65c8 100644
--- a/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c
+++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c
@@ -3,20 +3,63 @@
/* { dg-require-effective-target arm_fp16_ok } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_fp16_ieee } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
/* Test __fp16 arguments and return value in registers (hard-float). */
void
swap (__fp16, __fp16);
+/*
+** F:
+** ...
+** (
+
+Below block is for non-armv8.1
+** (
+** vmov\.f32 (s[3-9]|s1[0-5]), s0
+** ...
+** vmov\.f32 s0, s1
+** ...
+** vmov\.f32 s1, \1
+** |
+** vmov\.f32 (s[3-9]|s1[0-5]), s1
+** ...
+** vmov\.f32 s1, s0
+** ...
+** vmov\.f32 s0, \2
+** )
+** vstr\.32 s2, \[sp, #4\] @ int
+** bl swap
+** vldr\.32 s2, \[sp, #4\] @ int
+** vmov\.f32 s0, s2
+
+** |
+
+Below block is for armv8.1
+** (
+** vmov (s[3-9]|s1[0-5]), s0 @ __fp16
+** ...
+** vmov s0, s1 @ __fp16
+** ...
+** vmov s1, \3 @ __fp16
+** |
+** vmov (s[3-9]|s1[0-5]), s1 @ __fp16
+** ...
+** vmov s1, s0 @ __fp16
+** ...
+** vmov s0, \4 @ __fp16
+** )
+** vstr\.32 s2, \[sp, #4\] @ int
+** bl swap
+** vldr\.16 s0, \[sp, #4\]
+
+** )
+** ...
+*/
__fp16
F (__fp16 a, __fp16 b, __fp16 c)
{
swap (b, a);
return c;
}
-
-/* { dg-final { scan-assembler {vmov\.f32\ts[0-9]+, s1} } } */
-/* { dg-final { scan-assembler {vmov\.f32\ts1, s0} } } */
-/* { dg-final { scan-assembler {vmov\.f32\ts[0-9]+, s2+} } } */
-/* { dg-final { scan-assembler-times {vmov\.f32\ts0, s[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c
b/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c
index c34387f57828..48510e895368 100644
--- a/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c
+++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c
@@ -3,19 +3,42 @@
/* { dg-options "-mfloat-abi=softfp -O2 -mno-long-calls" } */
/* { dg-add-options arm_fp16_ieee } */
/* { dg-skip-if "incompatible float-abi" { arm*-*-* } { "-mfloat-abi=hard" } }
*/
+/* { dg-final { check-function-bodies "**" "" "" } } */
/* Test __fp16 arguments and return value in registers (softfp). */
void
swap (__fp16, __fp16);
+/*
+** F:
+** ...
+** (
+** mov r3, r0 @ __fp16
+** ...
+** mov r0, r1 @ __fp16
+** ...
+** mov r1, r3 @ __fp16
+** |
+** mov r3, r1 @ __fp16
+** ...
+** mov r1, r0 @ __fp16
+** ...
+** mov r0, r3 @ __fp16
+** )
+** ...
+*/
+/*
+** F: { target arm_little_endian }
+** ...
+** str r2, \[sp, #4\]
+** bl swap
+** ldrh r0, \[sp, #4\] @ __fp16
+** ...
+*/
__fp16
F (__fp16 a, __fp16 b, __fp16 c)
{
swap (b, a);
return c;
}
-
-/* { dg-final { scan-assembler-times {mov\tr[0-9]+, r[0-2]} 3 } } */
-/* { dg-final { scan-assembler-times {mov\tr1, r[03]} 1 } } */
-/* { dg-final { scan-assembler-times {mov\tr0, r[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c
b/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c
index 56a3ae261843..7238ef3a02e0 100644
--- a/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c
+++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c
@@ -3,21 +3,63 @@
/* { dg-require-effective-target arm_fp16_alternative_ok } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_fp16_alternative } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
/* Test __fp16 arguments and return value in registers (hard-float). */
void
swap (__fp16, __fp16);
+/*
+** F:
+** ...
+** (
+
+Below block is for non-armv8.1
+** (
+** vmov\.f32 (s[3-9]|s1[0-5]), s0
+** ...
+** vmov\.f32 s0, s1
+** ...
+** vmov\.f32 s1, \1
+** |
+** vmov\.f32 (s[3-9]|s1[0-5]), s1
+** ...
+** vmov\.f32 s1, s0
+** ...
+** vmov\.f32 s0, \2
+** )
+** vstr\.32 s2, \[sp, #4\] @ int
+** bl swap
+** vldr\.32 s2, \[sp, #4\] @ int
+** vmov\.f32 s0, s2
+
+** |
+
+Below block is for armv8.1
+** (
+** vmov (s[3-9]|s1[0-5]), s0
+** ...
+** vmov s0, s1
+** ...
+** vmov s1, \3
+** |
+** vmov (s[3-9]|s1[0-5]), s1
+** ...
+** vmov s1, s0
+** ...
+** vmov s0, \4
+** )
+** vstr\.32 s2, \[sp, #4\] @ int
+** bl swap
+** vldr\.16 s0, \[sp, #4\]
+
+** )
+** ...
+*/
__fp16
F (__fp16 a, __fp16 b, __fp16 c)
{
swap (b, a);
return c;
}
-
-/* { dg-final { scan-assembler {vmov\.f32\ts[0-9]+, s1} } } */
-/* { dg-final { scan-assembler {vmov\.f32\ts1, s0} } } */
-/* { dg-final { scan-assembler {vmov\.f32\ts[0-9]+, s2+} } } */
-/* { dg-final { scan-assembler-times {vmov\.f32\ts0, s[0-9]+} 2 } } */
-
diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c
b/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c
index daac29137aeb..13f08d8afa32 100644
--- a/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c
+++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-4.c
@@ -3,19 +3,42 @@
/* { dg-options "-mfloat-abi=softfp -O2" } */
/* { dg-add-options arm_fp16_alternative } */
/* { dg-skip-if "incompatible float-abi" { arm*-*-* } { "-mfloat-abi=hard" } }
*/
+/* { dg-final { check-function-bodies "**" "" "" } } */
/* Test __fp16 arguments and return value in registers (softfp). */
void
swap (__fp16, __fp16);
+/*
+** F:
+** ...
+** (
+** mov r3, r0 @ __fp16
+** ...
+** mov r0, r1 @ __fp16
+** ...
+** mov r1, r3 @ __fp16
+** |
+** mov r3, r1 @ __fp16
+** ...
+** mov r1, r0 @ __fp16
+** ...
+** mov r0, r3 @ __fp16
+** )
+** ...
+*/
+/*
+** F: { target arm_little_endian }
+** ...
+** str r2, \[sp, #4\]
+** bl swap
+** ldrh r0, \[sp, #4\] @ __fp16
+** ...
+*/
__fp16
F (__fp16 a, __fp16 b, __fp16 c)
{
swap (b, a);
return c;
}
-
-/* { dg-final { scan-assembler-times {mov\tr[0-9]+, r[0-2]} 3 } } */
-/* { dg-final { scan-assembler-times {mov\tr1, r[03]} 1 } } */
-/* { dg-final { scan-assembler-times {mov\tr0, r[0-9]+} 2 } } */
