https://gcc.gnu.org/g:6b1b02ef622788dd9beefa6f9bc4f845e971ffb6
commit 6b1b02ef622788dd9beefa6f9bc4f845e971ffb6
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Wed Oct 16 19:21:19 2024 -0400
Initial support for adding xxeval fusion support.
2024-10-16 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/fusion.md: Regenerate.
* config/rs6000/genfusion.pl (gen_logical_addsubf): Add support to
generate vector/vector logical fusion if XXEVAL supports the fusion.
* config/rs6000/predicates.md (vector_fusion_operand): New
predicate.
* config/rs6000/rs6000.cc (rs6000_opt_vars): Add -mxxeval.
* config/rs6000/rs6000.md (isa attribute): Add xxeval.
(enabled attribute): Add support for -mxxeval.
* config/rs6000/rs6000.opt (-mxxeval): New switch.
Diff:
---
gcc/config/rs6000/fusion.md | 782 +++++++++++++++++++++++-----------------
gcc/config/rs6000/genfusion.pl | 104 +++++-
gcc/config/rs6000/predicates.md | 14 +-
gcc/config/rs6000/rs6000.cc | 3 +
gcc/config/rs6000/rs6000.md | 7 +-
gcc/config/rs6000/rs6000.opt | 4 +
6 files changed, 586 insertions(+), 328 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index 4ed9ae1d69f4..724e4692d101 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -1871,146 +1871,170 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vand
(define_insn "*fuse_vand_vand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"%v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (and:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"%v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vand %3,%1,%0\;vand %3,%3,%2
vand %3,%1,%0\;vand %3,%3,%2
vand %3,%1,%0\;vand %3,%3,%2
- vand %4,%1,%0\;vand %3,%4,%2"
+ vand %4,%1,%0\;vand %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,1"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vand
(define_insn "*fuse_vandc_vand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;vand %3,%3,%2
vandc %3,%1,%0\;vand %3,%3,%2
vandc %3,%1,%0\;vand %3,%3,%2
- vandc %4,%1,%0\;vand %3,%4,%2"
+ vandc %4,%1,%0\;vand %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,2"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vand
(define_insn "*fuse_veqv_vand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
veqv %3,%1,%0\;vand %3,%3,%2
veqv %3,%1,%0\;vand %3,%3,%2
veqv %3,%1,%0\;vand %3,%3,%2
- veqv %4,%1,%0\;vand %3,%4,%2"
+ veqv %4,%1,%0\;vand %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,9"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vand
(define_insn "*fuse_vnand_vand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
- (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v")))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vnand %3,%1,%0\;vand %3,%3,%2
vnand %3,%1,%0\;vand %3,%3,%2
vnand %3,%1,%0\;vand %3,%3,%2
- vnand %4,%1,%0\;vand %3,%4,%2"
+ vnand %4,%1,%0\;vand %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,14"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vand
(define_insn "*fuse_vnor_vand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
- (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v")))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vnor %3,%1,%0\;vand %3,%3,%2
vnor %3,%1,%0\;vand %3,%3,%2
vnor %3,%1,%0\;vand %3,%3,%2
- vnor %4,%1,%0\;vand %3,%4,%2"
+ vnor %4,%1,%0\;vand %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,8"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vand
(define_insn "*fuse_vor_vand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vor %3,%1,%0\;vand %3,%3,%2
vor %3,%1,%0\;vand %3,%3,%2
vor %3,%1,%0\;vand %3,%3,%2
- vor %4,%1,%0\;vand %3,%4,%2"
+ vor %4,%1,%0\;vand %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,7"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vand
(define_insn "*fuse_vorc_vand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;vand %3,%3,%2
vorc %3,%1,%0\;vand %3,%3,%2
vorc %3,%1,%0\;vand %3,%3,%2
- vorc %4,%1,%0\;vand %3,%4,%2"
+ vorc %4,%1,%0\;vand %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,11"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vand
(define_insn "*fuse_vxor_vand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vxor %3,%1,%0\;vand %3,%3,%2
vxor %3,%1,%0\;vand %3,%3,%2
vxor %3,%1,%0\;vand %3,%3,%2
- vxor %4,%1,%0\;vand %3,%4,%2"
+ vxor %4,%1,%0\;vand %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,6"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vandc
@@ -2033,20 +2057,23 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vandc
(define_insn "*fuse_vandc_vandc"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;vandc %3,%3,%2
vandc %3,%1,%0\;vandc %3,%3,%2
vandc %3,%1,%0\;vandc %3,%3,%2
- vandc %4,%1,%0\;vandc %3,%4,%2"
+ vandc %4,%1,%0\;vandc %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,13"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vandc
@@ -2123,20 +2150,23 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vandc
(define_insn "*fuse_vorc_vandc"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;vandc %3,%3,%2
vorc %3,%1,%0\;vandc %3,%3,%2
vorc %3,%1,%0\;vandc %3,%3,%2
- vorc %4,%1,%0\;vandc %3,%4,%2"
+ vorc %4,%1,%0\;vandc %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,4"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vandc
@@ -2177,20 +2207,23 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> veqv
(define_insn "*fuse_vandc_veqv"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,v,wa"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;veqv %3,%3,%2
vandc %3,%1,%0\;veqv %3,%3,%2
vandc %3,%1,%0\;veqv %3,%3,%2
- vandc %4,%1,%0\;veqv %3,%4,%2"
+ vandc %4,%1,%0\;veqv %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,210"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> veqv
@@ -2267,20 +2300,23 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> veqv
(define_insn "*fuse_vorc_veqv"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,v,wa"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;veqv %3,%3,%2
vorc %3,%1,%0\;veqv %3,%3,%2
vorc %3,%1,%0\;veqv %3,%3,%2
- vorc %4,%1,%0\;veqv %3,%4,%2"
+ vorc %4,%1,%0\;veqv %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,75"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> veqv
@@ -2303,434 +2339,506 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vnand
(define_insn "*fuse_vand_vnand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (not:VM (and:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vand %3,%1,%0\;vnand %3,%3,%2
vand %3,%1,%0\;vnand %3,%3,%2
vand %3,%1,%0\;vnand %3,%3,%2
- vand %4,%1,%0\;vnand %3,%4,%2"
+ vand %4,%1,%0\;vnand %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,254"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vnand
(define_insn "*fuse_vandc_vnand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,v,wa"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;vnand %3,%3,%2
vandc %3,%1,%0\;vnand %3,%3,%2
vandc %3,%1,%0\;vnand %3,%3,%2
- vandc %4,%1,%0\;vnand %3,%4,%2"
+ vandc %4,%1,%0\;vnand %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,253"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vnand
(define_insn "*fuse_veqv_vnand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
veqv %3,%1,%0\;vnand %3,%3,%2
veqv %3,%1,%0\;vnand %3,%3,%2
veqv %3,%1,%0\;vnand %3,%3,%2
- veqv %4,%1,%0\;vnand %3,%4,%2"
+ veqv %4,%1,%0\;vnand %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,246"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vnand
(define_insn "*fuse_vnand_vnand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
- (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v"))))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,v,wa"))
+ (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vnand %3,%1,%0\;vnand %3,%3,%2
vnand %3,%1,%0\;vnand %3,%3,%2
vnand %3,%1,%0\;vnand %3,%3,%2
- vnand %4,%1,%0\;vnand %3,%4,%2"
+ vnand %4,%1,%0\;vnand %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,241"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vnand
(define_insn "*fuse_vnor_vnand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
- (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v"))))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,v,wa"))
+ (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vnor %3,%1,%0\;vnand %3,%3,%2
vnor %3,%1,%0\;vnand %3,%3,%2
vnor %3,%1,%0\;vnand %3,%3,%2
- vnor %4,%1,%0\;vnand %3,%4,%2"
+ vnor %4,%1,%0\;vnand %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,247"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vnand
(define_insn "*fuse_vor_vnand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (not:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vor %3,%1,%0\;vnand %3,%3,%2
vor %3,%1,%0\;vnand %3,%3,%2
vor %3,%1,%0\;vnand %3,%3,%2
- vor %4,%1,%0\;vnand %3,%4,%2"
+ vor %4,%1,%0\;vnand %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,248"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vnand
(define_insn "*fuse_vorc_vnand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,v,wa"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;vnand %3,%3,%2
vorc %3,%1,%0\;vnand %3,%3,%2
vorc %3,%1,%0\;vnand %3,%3,%2
- vorc %4,%1,%0\;vnand %3,%4,%2"
+ vorc %4,%1,%0\;vnand %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,244"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vnand
(define_insn "*fuse_vxor_vnand"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vxor %3,%1,%0\;vnand %3,%3,%2
vxor %3,%1,%0\;vnand %3,%3,%2
vxor %3,%1,%0\;vnand %3,%3,%2
- vxor %4,%1,%0\;vnand %3,%4,%2"
+ vxor %4,%1,%0\;vnand %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,249"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vnor
(define_insn "*fuse_vand_vnor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (not:VM (and:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vand %3,%1,%0\;vnor %3,%3,%2
vand %3,%1,%0\;vnor %3,%3,%2
vand %3,%1,%0\;vnor %3,%3,%2
- vand %4,%1,%0\;vnor %3,%4,%2"
+ vand %4,%1,%0\;vnor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,224"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vnor
(define_insn "*fuse_vandc_vnor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,v,wa"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;vnor %3,%3,%2
vandc %3,%1,%0\;vnor %3,%3,%2
vandc %3,%1,%0\;vnor %3,%3,%2
- vandc %4,%1,%0\;vnor %3,%4,%2"
+ vandc %4,%1,%0\;vnor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,208"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vnor
(define_insn "*fuse_veqv_vnor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
veqv %3,%1,%0\;vnor %3,%3,%2
veqv %3,%1,%0\;vnor %3,%3,%2
veqv %3,%1,%0\;vnor %3,%3,%2
- veqv %4,%1,%0\;vnor %3,%4,%2"
+ veqv %4,%1,%0\;vnor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,96"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vnor
(define_insn "*fuse_vnand_vnor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
- (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v"))))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,v,wa"))
+ (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vnand %3,%1,%0\;vnor %3,%3,%2
vnand %3,%1,%0\;vnor %3,%3,%2
vnand %3,%1,%0\;vnor %3,%3,%2
- vnand %4,%1,%0\;vnor %3,%4,%2"
+ vnand %4,%1,%0\;vnor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,16"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vnor
(define_insn "*fuse_vnor_vnor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
- (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v"))))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,v,wa"))
+ (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vnor %3,%1,%0\;vnor %3,%3,%2
vnor %3,%1,%0\;vnor %3,%3,%2
vnor %3,%1,%0\;vnor %3,%3,%2
- vnor %4,%1,%0\;vnor %3,%4,%2"
+ vnor %4,%1,%0\;vnor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,112"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vnor
(define_insn "*fuse_vor_vnor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (not:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vor %3,%1,%0\;vnor %3,%3,%2
vor %3,%1,%0\;vnor %3,%3,%2
vor %3,%1,%0\;vnor %3,%3,%2
- vor %4,%1,%0\;vnor %3,%4,%2"
+ vor %4,%1,%0\;vnor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,128"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vnor
(define_insn "*fuse_vorc_vnor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0
"altivec_register_operand" "v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0
"vector_fusion_operand" "v,v,v,v,wa"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;vnor %3,%3,%2
vorc %3,%1,%0\;vnor %3,%3,%2
vorc %3,%1,%0\;vnor %3,%3,%2
- vorc %4,%1,%0\;vnor %3,%4,%2"
+ vorc %4,%1,%0\;vnor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,64"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vnor
(define_insn "*fuse_vxor_vnor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (and:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vxor %3,%1,%0\;vnor %3,%3,%2
vxor %3,%1,%0\;vnor %3,%3,%2
vxor %3,%1,%0\;vnor %3,%3,%2
- vxor %4,%1,%0\;vnor %3,%4,%2"
+ vxor %4,%1,%0\;vnor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,144"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vor
(define_insn "*fuse_vand_vor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (and:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vand %3,%1,%0\;vor %3,%3,%2
vand %3,%1,%0\;vor %3,%3,%2
vand %3,%1,%0\;vor %3,%3,%2
- vand %4,%1,%0\;vor %3,%4,%2"
+ vand %4,%1,%0\;vor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,31"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vor
(define_insn "*fuse_vandc_vor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;vor %3,%3,%2
vandc %3,%1,%0\;vor %3,%3,%2
vandc %3,%1,%0\;vor %3,%3,%2
- vandc %4,%1,%0\;vor %3,%4,%2"
+ vandc %4,%1,%0\;vor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,47"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vor
(define_insn "*fuse_veqv_vor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
veqv %3,%1,%0\;vor %3,%3,%2
veqv %3,%1,%0\;vor %3,%3,%2
veqv %3,%1,%0\;vor %3,%3,%2
- veqv %4,%1,%0\;vor %3,%4,%2"
+ veqv %4,%1,%0\;vor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,159"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vor
(define_insn "*fuse_vnand_vor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
- (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v")))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vnand %3,%1,%0\;vor %3,%3,%2
vnand %3,%1,%0\;vor %3,%3,%2
vnand %3,%1,%0\;vor %3,%3,%2
- vnand %4,%1,%0\;vor %3,%4,%2"
+ vnand %4,%1,%0\;vor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,239"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vor
(define_insn "*fuse_vnor_vor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
- (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v")))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vnor %3,%1,%0\;vor %3,%3,%2
vnor %3,%1,%0\;vor %3,%3,%2
vnor %3,%1,%0\;vor %3,%3,%2
- vnor %4,%1,%0\;vor %3,%4,%2"
+ vnor %4,%1,%0\;vor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,143"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vor
(define_insn "*fuse_vor_vor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"%v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"%v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vor %3,%1,%0\;vor %3,%3,%2
vor %3,%1,%0\;vor %3,%3,%2
vor %3,%1,%0\;vor %3,%3,%2
- vor %4,%1,%0\;vor %3,%4,%2"
+ vor %4,%1,%0\;vor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,127"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vor
(define_insn "*fuse_vorc_vor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;vor %3,%3,%2
vorc %3,%1,%0\;vor %3,%3,%2
vorc %3,%1,%0\;vor %3,%3,%2
- vorc %4,%1,%0\;vor %3,%4,%2"
+ vorc %4,%1,%0\;vor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,191"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vor
(define_insn "*fuse_vxor_vor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vxor %3,%1,%0\;vor %3,%3,%2
vxor %3,%1,%0\;vor %3,%3,%2
vxor %3,%1,%0\;vor %3,%3,%2
- vxor %4,%1,%0\;vor %3,%4,%2"
+ vxor %4,%1,%0\;vor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,111"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vorc
@@ -2753,20 +2861,23 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vorc
(define_insn "*fuse_vandc_vorc"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;vorc %3,%3,%2
vandc %3,%1,%0\;vorc %3,%3,%2
vandc %3,%1,%0\;vorc %3,%3,%2
- vandc %4,%1,%0\;vorc %3,%4,%2"
+ vandc %4,%1,%0\;vorc %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,223"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vorc
@@ -2843,20 +2954,23 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vorc
(define_insn "*fuse_vorc_vorc"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (not:VM (match_operand:VM 2 "altivec_register_operand"
"v,v,v,v"))))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (ior:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (not:VM (match_operand:VM 2 "vector_fusion_operand"
"v,v,v,v,wa"))))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;vorc %3,%3,%2
vorc %3,%1,%0\;vorc %3,%3,%2
vorc %3,%1,%0\;vorc %3,%3,%2
- vorc %4,%1,%0\;vorc %3,%4,%2"
+ vorc %4,%1,%0\;vorc %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,79"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vorc
@@ -2879,146 +2993,170 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vand -> vxor
(define_insn "*fuse_vand_vxor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (xor:VM (and:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vand %3,%1,%0\;vxor %3,%3,%2
vand %3,%1,%0\;vxor %3,%3,%2
vand %3,%1,%0\;vxor %3,%3,%2
- vand %4,%1,%0\;vxor %3,%4,%2"
+ vand %4,%1,%0\;vxor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,30"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vxor
(define_insn "*fuse_vandc_vxor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (xor:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vandc %3,%1,%0\;vxor %3,%3,%2
vandc %3,%1,%0\;vxor %3,%3,%2
vandc %3,%1,%0\;vxor %3,%3,%2
- vandc %4,%1,%0\;vxor %3,%4,%2"
+ vandc %4,%1,%0\;vxor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,45"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vxor
(define_insn "*fuse_veqv_vxor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v")))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (xor:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
veqv %3,%1,%0\;vxor %3,%3,%2
veqv %3,%1,%0\;vxor %3,%3,%2
veqv %3,%1,%0\;vxor %3,%3,%2
- veqv %4,%1,%0\;vxor %3,%4,%2"
+ veqv %4,%1,%0\;vxor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,150"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnand -> vxor
(define_insn "*fuse_vnand_vxor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
- (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v")))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (xor:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vnand %3,%1,%0\;vxor %3,%3,%2
vnand %3,%1,%0\;vxor %3,%3,%2
vnand %3,%1,%0\;vxor %3,%3,%2
- vnand %4,%1,%0\;vxor %3,%4,%2"
+ vnand %4,%1,%0\;vxor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,225"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vnor -> vxor
(define_insn "*fuse_vnor_vxor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
- (not:VM (match_operand:VM 1
"altivec_register_operand" "v,v,v,v")))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (xor:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (not:VM (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa")))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vnor %3,%1,%0\;vxor %3,%3,%2
vnor %3,%1,%0\;vxor %3,%3,%2
vnor %3,%1,%0\;vxor %3,%3,%2
- vnor %4,%1,%0\;vxor %3,%4,%2"
+ vnor %4,%1,%0\;vxor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,135"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vor -> vxor
(define_insn "*fuse_vor_vxor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (xor:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vor %3,%1,%0\;vxor %3,%3,%2
vor %3,%1,%0\;vxor %3,%3,%2
vor %3,%1,%0\;vxor %3,%3,%2
- vor %4,%1,%0\;vxor %3,%4,%2"
+ vor %4,%1,%0\;vxor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,120"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vorc -> vxor
(define_insn "*fuse_vorc_vxor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (xor:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 1 "vector_fusion_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vorc %3,%1,%0\;vxor %3,%3,%2
vorc %3,%1,%0\;vxor %3,%3,%2
vorc %3,%1,%0\;vxor %3,%3,%2
- vorc %4,%1,%0\;vxor %3,%4,%2"
+ vorc %4,%1,%0\;vxor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,180"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vxor
(define_insn "*fuse_vxor_vxor"
- [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
- (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
- (match_operand:VM 1 "altivec_register_operand"
"%v,v,v,v"))
- (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
- (clobber (match_scratch:VM 4 "=X,X,X,&v"))]
+ [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,v,wa")
+ (xor:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vector_fusion_operand"
"%v,v,v,v,wa"))
+ (match_operand:VM 2 "vector_fusion_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
"(TARGET_P10_FUSION)"
"@
vxor %3,%1,%0\;vxor %3,%3,%2
vxor %3,%1,%0\;vxor %3,%3,%2
vxor %3,%1,%0\;vxor %3,%3,%2
- vxor %4,%1,%0\;vxor %3,%4,%2"
+ vxor %4,%1,%0\;vxor %3,%4,%2
+ xxeval %x3,%x2,%x1,%x0,105"
[(set_attr "type" "fused_vector")
(set_attr "cost" "6")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
;; add-add fusion pattern generated by gen_addadd
(define_insn "*fuse_add_add"
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 2271be14bfa4..57ae80ace51c 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -211,25 +211,78 @@ sub gen_logical_addsubf
$inner_comp, $inner_inv, $inner_rtl, $inner_op, $both_commute, $c4,
$bc, $inner_arg0, $inner_arg1, $inner_exp, $outer_arg2, $outer_exp,
$ftype, $insn, $is_subf, $is_rsubf, $outer_32, $outer_42,$outer_name,
- $fuse_type);
- KIND: foreach $kind ('scalar','vector') {
+ $fuse_type, $xxeval, $c5, $vect_pred, $vect_inner_arg0,
$vect_inner_arg1,
+ $vect_inner_exp, $vect_outer_arg2, $vect_outer_exp);
+
+ my %xxeval_fusions = (
+ "vand_vand" => 1,
+ "vandc_vand" => 2,
+ "vorc_vandc" => 4,
+ "vxor_vand" => 6,
+ "vor_vand" => 7,
+ "vnor_vand" => 8,
+ "veqv_vand" => 9,
+ "vorc_vand" => 11,
+ "vandc_vandc" => 13,
+ "vnand_vand" => 14,
+ "vnand_vnor" => 16,
+ "vand_vxor" => 30,
+ "vand_vor" => 31,
+ "vandc_vxor" => 45,
+ "vandc_vor" => 47,
+ "vorc_vnor" => 64,
+ "vorc_veqv" => 75,
+ "vorc_vorc" => 79,
+ "veqv_vnor" => 96,
+ "vxor_vxor" => 105,
+ "vxor_vor" => 111,
+ "vnor_vnor" => 112,
+ "vor_vxor" => 120,
+ "vor_vor" => 127,
+ "vor_vnor" => 128,
+ "vnor_vxor" => 135,
+ "vnor_vor" => 143,
+ "vxor_vnor" => 144,
+ "veqv_vxor" => 150,
+ "veqv_vor" => 159,
+ "vorc_vxor" => 180,
+ "vorc_vor" => 191,
+ "vandc_vnor" => 208,
+ "vandc_veqv" => 210,
+ "vandc_vorc" => 223,
+ "vand_vnor" => 224,
+ "vnand_vxor" => 225,
+ "vnand_vor" => 239,
+ "vnand_vnand" => 241,
+ "vorc_vnand" => 244,
+ "veqv_vnand" => 246,
+ "vnor_vnand" => 247,
+ "vor_vnand" => 248,
+ "vxor_vnand" => 249,
+ "vandc_vnand" => 253,
+ "vand_vnand" => 254,
+ );
+
+ KIND: foreach $kind ('scalar','vector') {
@outer_ops = @logicals;
if ( $kind eq 'vector' ) {
$vchr = "v";
$mode = "VM";
$pred = "altivec_register_operand";
+ $vect_pred = "vector_fusion_operand";
$constraint = "v";
$fuse_type = "fused_vector";
} else {
$vchr = "";
$mode = "GPR";
- $pred = "gpc_reg_operand";
+ $vect_pred = $pred = "gpc_reg_operand";
$constraint = "r";
$fuse_type = "fused_arith_logical";
push (@outer_ops, @addsub);
push (@outer_ops, ( "rsubf" ));
}
$c4 = "${constraint},${constraint},${constraint},${constraint}";
+ $c5 = "${constraint},${constraint},${constraint},${constraint},wa";
OUTER: foreach $outer ( @outer_ops ) {
$outer_name = "${vchr}${outer}";
$is_subf = ( $outer eq "subf" );
@@ -257,29 +310,40 @@ sub gen_logical_addsubf
$inner_inv = $invert{$inner};
$inner_rtl = $rtlop{$inner};
$inner_op = "${vchr}${inner}";
+
# If both ops commute then we can specify % on operand 1
# so the pattern will let operands 1 and 2 interchange.
$both_commute = ($inner eq $outer) && ($commute2{$inner} == 1);
$bc = ""; if ( $both_commute ) { $bc = "%"; }
$inner_arg0 = "(match_operand:${mode} 0 \"${pred}\" \"${c4}\")";
$inner_arg1 = "(match_operand:${mode} 1 \"${pred}\" \"${bc}${c4}\")";
+ $vect_inner_arg0 = "(match_operand:${mode} 0 \"${vect_pred}\"
\"${c5}\")";
+ $vect_inner_arg1 = "(match_operand:${mode} 1 \"${vect_pred}\"
\"${bc}${c5}\")";
if ( ($inner_comp & 1) == 1 ) {
$inner_arg0 = "(not:${mode} $inner_arg0)";
+ $vect_inner_arg0 = "(not:${mode} $vect_inner_arg0)";
}
if ( ($inner_comp & 2) == 2 ) {
$inner_arg1 = "(not:${mode} $inner_arg1)";
+ $vect_inner_arg1 = "(not:${mode} $vect_inner_arg1)";
}
$inner_exp = "(${inner_rtl}:${mode} ${inner_arg0}
${inner_arg1})";
+ $vect_inner_exp = "(${inner_rtl}:${mode} ${vect_inner_arg0}
+ ${vect_inner_arg1})";
if ( $inner_inv == 1 ) {
$inner_exp = "(not:${mode} $inner_exp)";
+ $vect_inner_exp = "(not:${mode} $vect_inner_exp)";
}
$outer_arg2 = "(match_operand:${mode} 2 \"${pred}\" \"${c4}\")";
+ $vect_outer_arg2 = "(match_operand:${mode} 2 \"${vect_pred}\"
\"${c5}\")";
if ( ($outer_comp & 1) == 1 ) {
$outer_arg2 = "(not:${mode} $outer_arg2)";
+ $vect_outer_arg2 = "(not:${mode} $vect_outer_arg2)";
}
if ( ($outer_comp & 2) == 2 ) {
$inner_exp = "(not:${mode} $inner_exp)";
+ $vect_inner_exp = "(not:${mode} $vect_inner_exp)";
}
if ( $is_subf ) {
$outer_32 = "%2,%3";
@@ -291,15 +355,23 @@ sub gen_logical_addsubf
if ( $is_rsubf == 1 ) {
$outer_exp = "(${outer_rtl}:${mode} ${outer_arg2}
${inner_exp})";
+ $vect_outer_exp = "(${outer_rtl}:${mode} ${vect_outer_arg2}
+ ${vect_inner_exp})";
} else {
$outer_exp = "(${outer_rtl}:${mode} ${inner_exp}
${outer_arg2})";
+ $vect_outer_exp = "(${outer_rtl}:${mode} ${vect_inner_exp}
+ ${vect_outer_arg2})";
}
if ( $outer_inv == 1 ) {
$outer_exp = "(not:${mode} $outer_exp)";
+ $vect_outer_exp = "(not:${mode} $vect_outer_exp)";
}
- $insn = <<"EOF";
+ # See if we can use xxeval on vector fusion
+ $xxeval = $xxeval_fusions{"${inner_op}_${outer_name}"};
+ if (!$xxeval) {
+ $insn = <<"EOF";
;; $ftype fusion pattern generated by gen_logical_addsubf
;; $kind $inner_op -> $outer_name
@@ -318,6 +390,30 @@ sub gen_logical_addsubf
(set_attr "length" "8")])
EOF
+ } else {
+ $insn = <<"EOF";
+
+;; $ftype fusion pattern generated by gen_logical_addsubf
+;; $kind $inner_op -> $outer_name
+(define_insn "*fuse_${inner_op}_${outer_name}"
+ [(set (match_operand:${mode} 3 "${vect_pred}"
"=&0,&1,&${constraint},${constraint},wa")
+ ${vect_outer_exp})
+ (clobber (match_scratch:${mode} 4 "=X,X,X,&${constraint},X"))]
+ "(TARGET_P10_FUSION)"
+ "@
+ ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32}
+ ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32}
+ ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32}
+ ${inner_op} %4,%1,%0\\;${outer_op} %3,${outer_42}
+ xxeval %x3,%x2,%x1,%x0,${xxeval}"
+ [(set_attr "type" "$fuse_type")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")
+ (set_attr "isa" "*,*,*,*,xxeval")])
+EOF
+ }
+
print $insn;
}
}
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 0b78901e94be..1d95e34557e5 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -82,7 +82,7 @@
return ALTIVEC_REGNO_P (REGNO (op));
})
-;; Return 1 if op is a VSX register.
+;; Return 1 if op is a VSX register
(define_predicate "vsx_register_operand"
(match_operand 0 "register_operand")
{
@@ -119,6 +119,18 @@
return VSX_REGNO_P (REGNO (op));
})
+;; Return 1 if op is a register that can be used for vector fusion. If XXEVAL
+;; is supported, return true for all VSX registers, otherwise the fusion is
+;; limited to Altivec registers since the machine only fuses Altivec
+;; operations.
+(define_predicate "vector_fusion_operand"
+ (match_operand 0 "register_operand")
+{
+ return (TARGET_XXEVAL && TARGET_PREFIXED
+ ? vsx_register_operand (op, mode)
+ : altivec_register_operand (op, mode));
+})
+
;; Return 1 if op is a vector register that operates on floating point vectors
;; (either altivec or VSX).
(define_predicate "vfloat_operand"
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index aa67e7256bb9..072556b7fd7a 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -24668,6 +24668,9 @@ static struct rs6000_opt_var const rs6000_opt_vars[] =
{ "speculate-indirect-jumps",
offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
+ { "xxeval",
+ offsetof (struct gcc_options, x_TARGET_XXEVAL),
+ offsetof (struct cl_target_option, x_TARGET_XXEVAL), },
};
/* Inner function to handle attribute((target("..."))) and #pragma GCC target
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 6642a4717963..68fbfec95546 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -369,7 +369,7 @@
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,xxeval"
(const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -421,6 +421,11 @@
(and (eq_attr "isa" "p10")
(match_test "TARGET_POWER10"))
(const_int 1)
+
+ (and (eq_attr "isa" "xxeval")
+ (match_test "TARGET_PREFIXED && TARGET_XXEVAL"))
+ (const_int 1)
+
] (const_int 0)))
;; If this instruction is microcoded on the CELL processor
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 0d71dbaf2fc1..cfd81a177a6e 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -631,6 +631,10 @@ mieee128-constant
Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
Generate (do not generate) code that uses the LXVKQ instruction.
+mxxeval
+Target Undocumented Var(TARGET_XXEVAL) Init(1) Save
+Generate (do not generate) code that uses the XXEVAL instruction.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
