https://gcc.gnu.org/g:40636facc4f89efc136859f9e72338cb7dba6ed4
commit 40636facc4f89efc136859f9e72338cb7dba6ed4
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Wed Oct 16 03:27:19 2024 -0400
Initial support for adding xxeval fusion support.
2024-10-16 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/fusion.md (fuse_vandc_xor_noxxeval): Rename from
fuse_vandc_xor, and restrict the case to non-xxeval support.
(fuse_vandc_vxor_xxeval): New insn.
(fuse_vxor_vxor_noxxeval): Rename from fuse_vxor_xor, and restrict
the
case to non-xxeval support.
(fuse_vxor_vxor_xxeval): New insn.
* config/rs6000/rs6000.cc (rs6000_opt_vars): Add -mxxeval.
* config/rs6000/rs6000.opt (-mxxeval): New switch.
Diff:
---
gcc/config/rs6000/fusion.md | 44 ++++++++++++++++++++++++++++++++++++++++----
gcc/config/rs6000/rs6000.cc | 3 +++
gcc/config/rs6000/rs6000.opt | 4 ++++
3 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index 4ed9ae1d69f4..5332c84681fa 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -2896,13 +2896,13 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vandc -> vxor
-(define_insn "*fuse_vandc_vxor"
+(define_insn "*fuse_vandc_vxor_noxxeval"
[(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
(xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v"))
(match_operand:VM 1 "altivec_register_operand"
"v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&v"))]
- "(TARGET_P10_FUSION)"
+ "(TARGET_P10_FUSION && (!TARGET_XXEVAL || !TARGET_PREFIXED))"
"@
vandc %3,%1,%0\;vxor %3,%3,%2
vandc %3,%1,%0\;vxor %3,%3,%2
@@ -2912,6 +2912,24 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
+(define_insn "*fuse_vandc_vxor_xxeval"
+ [(set (match_operand:VM 3 "vsx_register_operand" "=&0,&1,&v,v,wa")
+ (xor:VM (and:VM (not:VM (match_operand:VM 0 "vsx_register_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 1 "vsx_register_operand"
"v,v,v,v,wa"))
+ (match_operand:VM 2 "vsx_register_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
+ "(TARGET_P10_FUSION && TARGET_XXEVAL && TARGET_PREFIXED)"
+ "@
+ vandc %3,%1,%0\;vxor %3,%3,%2
+ vandc %3,%1,%0\;vxor %3,%3,%2
+ vandc %3,%1,%0\;vxor %3,%3,%2
+ vandc %4,%1,%0\;vxor %3,%4,%2
+ xxeval %w3,%w0,%w1,%w2,45\t\t# fuse xxlxor (%w0, xxlandc (%x1, %x2))"
+ [(set_attr "type" "fused_vector")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")])
+
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector veqv -> vxor
(define_insn "*fuse_veqv_vxor"
@@ -3004,13 +3022,13 @@
;; logical-logical fusion pattern generated by gen_logical_addsubf
;; vector vxor -> vxor
-(define_insn "*fuse_vxor_vxor"
+(define_insn "*fuse_vxor_vxor_noxxeval"
[(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v")
(xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand"
"v,v,v,v")
(match_operand:VM 1 "altivec_register_operand"
"%v,v,v,v"))
(match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
(clobber (match_scratch:VM 4 "=X,X,X,&v"))]
- "(TARGET_P10_FUSION)"
+ "(TARGET_P10_FUSION && (!TARGET_XXEVAL || !TARGET_PREFIXED))"
"@
vxor %3,%1,%0\;vxor %3,%3,%2
vxor %3,%1,%0\;vxor %3,%3,%2
@@ -3020,6 +3038,24 @@
(set_attr "cost" "6")
(set_attr "length" "8")])
+(define_insn "*fuse_vxor_vxor_xxeval"
+ [(set (match_operand:VM 3 "vsx_register_operand" "=&0,&1,&v,v,wa")
+ (xor:VM (xor:VM (match_operand:VM 0 "vsx_register_operand"
"v,v,v,v,wa")
+ (match_operand:VM 1 "vsx_register_operand"
"%v,v,v,v,wa"))
+ (match_operand:VM 2 "vsx_register_operand" "v,v,v,v,wa")))
+ (clobber (match_scratch:VM 4 "=X,X,X,&v,X"))]
+ "(TARGET_P10_FUSION && TARGET_XXEVAL && TARGET_PREFIXED)"
+ "@
+ vxor %3,%1,%0\;vxor %3,%3,%2
+ vxor %3,%1,%0\;vxor %3,%3,%2
+ vxor %3,%1,%0\;vxor %3,%3,%2
+ vxor %4,%1,%0\;vxor %3,%4,%2
+ xxeval %x3,%x0,%x1,%x2,105\t\t# fuse xxlxor (%x0, xxlxor (%x1,%x2))"
+ [(set_attr "type" "fused_vector")
+ (set_attr "cost" "6")
+ (set_attr "length" "8")
+ (set_attr "prefixed" "*,*,*,*,yes")])
+
;; add-add fusion pattern generated by gen_addadd
(define_insn "*fuse_add_add"
[(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r")
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index aa67e7256bb9..072556b7fd7a 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -24668,6 +24668,9 @@ static struct rs6000_opt_var const rs6000_opt_vars[] =
{ "speculate-indirect-jumps",
offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
+ { "xxeval",
+ offsetof (struct gcc_options, x_TARGET_XXEVAL),
+ offsetof (struct cl_target_option, x_TARGET_XXEVAL), },
};
/* Inner function to handle attribute((target("..."))) and #pragma GCC target
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 0d71dbaf2fc1..127befdcd56b 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -631,6 +631,10 @@ mieee128-constant
Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
Generate (do not generate) code that uses the LXVKQ instruction.
+mxxeval
+Target Var(TARGET_XXEVAL) Init(0) Save
+Use xxeval for fusion
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
