https://gcc.gnu.org/g:762bfe72ee49bd65474216af729118bc94272d1a
commit 762bfe72ee49bd65474216af729118bc94272d1a
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Mon Aug 12 17:41:16 2024 -0400
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.bugs | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index e8b978dd3d0f..27759bef3284 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,3 +1,59 @@
+==================== Branch work175-bugs, patch #310 ====================
+
+Optimize vec_splats of vec_extract for V2DI/V2DF (PR target/99293)
+
+This patch optimizes cases like:
+
+ vector double v1, v2;
+ /* ... */
+ v2 = vec_splats (vec_extract (v1, 0); /* or */
+ v2 = vec_splats (vec_extract (v1, 1);
+
+Previously:
+
+ vector long long
+ splat_dup_l_0 (vector long long v)
+ {
+ return __builtin_vec_splats (__builtin_vec_extract (v, 0));
+ }
+
+would generate:
+
+ mfvsrld 9,34
+ mtvsrdd 34,9,9
+ blr
+
+With this patch, GCC generates:
+
+ xxpermdi 34,34,34,3
+ blr
+
+
+I have tested this patch on the following systems and there was no degration.
+Can I check it into the trunk branch?
+
+ * Power10, LE, --with-cpu=power10, IBM 128-bit long double
+ * Power9, LE, --with-cpu=power9, IBM 128-bit long double
+ * Power9, LE, --with-cpu=power9, IEEE 128-bit long double
+ * Power9, LE, --with-cpu=power9, 64-bit default long double
+ * Power9, BE, --with-cpu=power9, IBM 128-bit long double
+ * Power8, BE, --with-cpu=power8, IBM 128-bit long double
+
+2024-08-12 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ PR target/99293
+ * gcc/config/rs6000/vsx.md (vsx_splat_extract_<mode>): New combiner
+ insn.
+
+gcc/testsuite/
+
+ PR target/108958
+ * gcc.target/powerpc/pr99293.c: New test.
+ * gcc.target/powerpc/builtins-1.c: Update insn count.
+
+
==================== Branch work175-bugs, patch #303 ====================
Do not add -mvsx when testing the float128 support.
