https://gcc.gnu.org/g:42f6f1cdec43877fd0532acd297deba0aec5c3c2
commit 42f6f1cdec43877fd0532acd297deba0aec5c3c2
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Tue Jun 4 14:29:19 2024 -0400
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.tar | 248 +++++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 247 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar
index c512209738a..a69b0f59eac 100644
--- a/gcc/ChangeLog.tar
+++ b/gcc/ChangeLog.tar
@@ -1,6 +1,252 @@
+==================== Branch work168-tar, patch #201 ====================
+
+Add support for the TAR register.
+
+2024-06-04 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/constraints.md (h constraint): Add TAR register to the
+ documentation.
+ (wt constraint): New constraint.
+ * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Document that we
+ do not explicitly add -mtar for power9.
+ (OTHER_POWER10_MASKS): Add -mtar.
+ (POWERPC_MASKS): Likewise.
+ * config/rs6000/rs6000.cc (rs6000_reg_names): Add TAR register support.
+ (alt_reg_names): Likewise.
+ (rs6000_hard_regno_mode_ok_uncached): Likewise.
+ (rs6000_debug_reg_global): Print the register class that wt maps too.
+ (rs6000_init_hard_regno_mode_ok): Add TAR register support.
+ (rs6000_option_override_internal): Restrict -mtar to power9 and above.
+ (rs6000_conditional_register_usage): Add TAR register support.
+ (print_operand): Likewise.
+ (rs6000_debugger_regno): Likewise.
+ (rs6000_opt_masks): Add support for -mtar.
+ * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Add TAR register
+ support.
+ (FIXED_REGISTERS): Likewise.
+ (CALL_REALLY_USED_REGISTERS): Likewise.
+ (REG_ALLOC_ORDER): Likewise.
+ (enum reg_class): Likewise.
+ (REG_CLASS_NAMES): Likewise.
+ (REG_CLASS_CONTENTS): Likewise.
+ (enum r6000_reg_class_enum): Add support for the wt constraint.
+ * config/rs6000/rs6000.md (TAR_REGNO): New constant.
+ (mov<mode>_internal): Add TAR register support.
+ (call_indirect_nonlocal_sysv<mode>): Likewise.
+ (call_value_indirect_nonlocal_sysv<mode>): Likewise.
+ (call_indirect_aix<mode>): Likewise.
+ (call_value_indirect_aix<mode>): Likewise.
+ (call_indirect_elfv2<mode>): Likewise.
+ (call_indirect_pcrel<mode>): Likewise.
+ (call_value_indirect_elfv2<mode>): Likewise.
+ (call_value_indirect_pcrel<mode>): Likewise.
+ (*sibcall_indirect_nonlocal_sysv<mode>): Likewise.
+ (sibcall_value_indirect_nonlocal_sysv<mode>): Likewise.
+ (indirect_jump<mode>): Likewise.
+ (@indirect_jump<mode>_nospec): Likewise.
+ (@tablejump<mode>_insn_normal): Likewise.
+ (@tablejump<mode>_insn_nospec): Likewise.
+ * config/rs6000/rs6000.opt (-mtar): New option.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/ppc-switch-1.c: Update test for the TAR register.
+ * gcc.target/powerpc/pr51513.c: Likewise.
+ * gcc.target/powerpc/safe-indirect-jump-2.c: Likewise.
+ * gcc.target/powerpc/safe-indirect-jump-3.c: Likewise.
+ * gcc.target/powerpc/tar-register.c: New test.
+
+==================== Branch work168-tar, patch #200 ====================
+
+Restrict SPR to appropriate integer modes.
+
+In preparation for the patches to add support for the TAR register, I
restricted
+the modes that special purpose registers (SPRs) could hold to be appropriate
+sized scalar integers. I have discovered occasionally when GCC has run out of
+registers, it will use the SPRs to hold values instead of spilling them to the
+stack. The LR/CTR registers can hold 8/16/32-bit values and on 64-bit systems,
+they can also hold 64-bit values. The VRSAVE and VSCR registers can only hold
+32-bit values.
+
+2024-06-04 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Restrict
+ SPR registers to only hold scalar integer modes of an appropriate size.
+ * config/rs6000/rs6000.md (movcc_<mode>): Remove alternatives that move
+ values to/from the SPRs.
+ (movsf_hardfloat): Likewise.
+ (movsd_hardfloat): Likewise.
+ (mov<mode>_softfloat): Likewise.
+ (mov<mode>_softfloat32): Likewise.
+ (mov<mode>_hardfloat64): Likewise.
+ (*mov<mode>_softfloat64): Likewise.
+
+==================== Branch work168-tar, patch #11 from work168 branch
====================
+
+Add -mcpu=future tuning support.
+
+This patch makes -mtune=future use the same tuning decision as -mtune=power11.
+
+2024-06-03 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/power10.md (all reservations): Add future as an
+ alterntive to power10 and power11.
+
+==================== Branch work168-tar, patch #10 from work168 branch
====================
+
+Add -mcpu=future support.
+
+This patch adds the future option to the -mcpu= and -mtune= switches.
+
+This patch treats the future like a power11 in terms of costs and reassociation
+width.
+
+This patch issues a ".machine future" to the assembly file if you use
+-mcpu=power11.
+
+This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future.
+
+This patch allows GCC to be configured with the --with-cpu=future and
+--with-tune=future options.
+
+This patch passes -mfuture to the assembler if the user uses -mcpu=future.
+
+2024-06-03 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
+ * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11.
+ * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+ * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+ * config/rs6000/driver-rs6000.cc (asm_names): Likewise.
+ * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+ _ARCH_PWR_FUTURE if -mcpu=future.
+ * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define.
+ (POWERPC_MASKS): Add future isa bit.
+ (power11 cpu): Add future definition.
+ * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor.
+ * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
+ * config/rs6000/rs6000-tables.opt: Regenerate.
+ * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future
+ support.
+ (rs6000_machine_from_flags): Likewise.
+ (rs6000_reassociation_width): Likewise.
+ (rs6000_adjust_cost): Likewise.
+ (rs6000_issue_rate): Likewise.
+ (rs6000_sched_reorder): Likewise.
+ (rs6000_sched_reorder2): Likewise.
+ (rs6000_register_move_cost): Likewise.
+ (rs6000_opt_masks): Likewise.
+ * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
+ * config/rs6000/rs6000.md (cpu attribute): Add future.
+ * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag.
+ * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future.
+
+==================== Branch work168-tar, patch #3 from work168 branch
====================
+
+Add -mcpu=power11 tests.
+
+This patch adds some simple tests for -mcpu=power11 support. In order to run
+these tests, you need an assembler that supports the appropriate option for
+supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX).
+
+2024-06-03 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/power11-1.c: New test.
+ * gcc.target/powerpc/power11-2.c: Likewise.
+ * gcc.target/powerpc/power11-3.c: Likewise.
+ * lib/target-supports.exp (check_effective_target_power11_ok): Add new
+ effective target.
+
+==================== Branch work168-tar, patch #2 from work168 branch
====================
+
+Add -mcpu=power11 tuning support.
+
+This patch makes -mtune=power11 use the same tuning decisions as
-mtune=power10.
+
+2024-06-03 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/power10.md (all reservations): Add power11 as an
+ alternative to power10.
+
+==================== Branch work168-tar, patch #1 from work168 branch
====================
+
+Add -mcpu=power11 support.
+
+This patch adds the power11 option to the -mcpu= and -mtune= switches.
+
+This patch treats the power11 like a power10 in terms of costs and
reassociation
+width.
+
+This patch issues a ".machine power11" to the assembly file if you use
+-mcpu=power11.
+
+This patch defines _ARCH_PWR11 if the user uses -mcpu=power11.
+
+This patch allows GCC to be configured with the --with-cpu=power11 and
+--with-tune=power11 options.
+
+This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11.
+
+This patch adds support for using "power11" in the __builtin_cpu_is built-in
+function.
+
+2024-06-03 Michael Meissner <meiss...@linux.ibm.com>
+
+gcc/
+
+ * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
+ * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11.
+ * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+ * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+ * config/rs6000/driver-rs6000.cc (asm_names): Likewise.
+ * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define.
+ * config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11.
+ * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+ _ARCH_PWR11 if -mcpu=power11.
+ * config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New define.
+ (POWERPC_MASKS): Add power11 isa bit.
+ (power11 cpu): Add power11 definition.
+ * config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11
processor.
+ * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
+ * config/rs6000/rs6000-tables.opt: Regenerate.
+ * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add power11
+ support.
+ (rs6000_machine_from_flags): Likewise.
+ (rs6000_reassociation_width): Likewise.
+ (rs6000_adjust_cost): Likewise.
+ (rs6000_issue_rate): Likewise.
+ (rs6000_sched_reorder): Likewise.
+ (rs6000_sched_reorder2): Likewise.
+ (rs6000_register_move_cost): Likewise.
+ (rs6000_opt_masks): Likewise.
+ * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
+ * config/rs6000/rs6000.md (cpu attribute): Add power11.
+ * config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA flag.
+ * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11.
+
==================== Branch work168-tar, baseline ====================
2024-06-03 Michael Meissner <meiss...@linux.ibm.com>
- Clone branch
+Add ChangeLog.tar and update REVISION.
+
+2024-06-03 Michael Meissner <meiss...@linux.ibm.com>
+gcc/
+
+ * ChangeLog.tar: New file for branch.
+ * REVISION: Update.
+
+ Clone branch
