[Bug target/128242] Incorrect handling of vector shift counts with widening shifts on RISC-V

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=128242

--- Comment #1 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Related, LLM pointed out this pattern may have a similar kind of issue:

(define_insn_and_split "*vwsll_zext1_trunc_<mode>"
  [(set (match_operand:<V_DOUBLE_TRUNC> 0   "register_operand"     "=vr ")
    (truncate:<V_DOUBLE_TRUNC>
      (ashift:VQEXTI
        (zero_extend:VQEXTI
          (match_operand:<V_QUAD_TRUNC> 1   "register_operand"     " vr "))
        (match_operand:VQEXTI           2   "vector_shift_operand" "vrvk"))))]
  "TARGET_ZVBB && can_create_pseudo_p ()"
  "#"
  "&& 1"
  [(const_int 0)]
  {
    rtx truncated = gen_reg_rtx (<V_QUAD_TRUNC>mode);
    emit_insn (gen_trunc<mode><v_quad_trunc>2 (truncated, operands[2]));
    operands[2] = truncated;

    insn_code icode = code_for_pred_vwsll (<V_DOUBLE_TRUNC>mode);
    riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
    DONE;
  }
  [(set_attr "type" "vwsll")])