https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114134

--- Comment #16 from Uroš Bizjak <ubizjak at gmail dot com> ---
Comment on attachment 65015
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=65015
A patch

>+(define_insn "*fix_trunc<MODEF:mode>si_sse_zext"
>+  [(set (match_operand:DI 0 "register_operand" "=r,r")
>+          (zero_extend:DI
>+          (fix:SI (match_operand:MODEF 1 "nonimmediate_operand" "v,m"))))]
>+  "SSE_FLOAT_MODE_P (<MODEF:MODE>mode)
>+   && (!TARGET_FISTTP || TARGET_SSE_MATH)"
>+  "%vcvtt<MODEF:ssemodesuffix>2sil\t{%1, %k0|%k0, %1}"
>+  [(set_attr "type" "sseicvt")
>+   (set_attr "prefix" "maybe_vex")
>+   (set_attr "prefix_rex" "*")
>+   (set_attr "mode" "<MODEF:MODE>")
>+   (set_attr "athlon_decode" "double,vector")
>+   (set_attr "amdfam10_decode" "double,double")
>+   (set_attr "bdver1_decode" "double,double")])

This pattern is valid for TARGET_64BIT only.

Reply via email to