https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123484

--- Comment #5 from Hongtao Liu <liuhongt at gcc dot gnu.org> ---
(In reply to Jakub Jelinek from comment #4)
> I would say the problem is in "divv4hf3" being guarded with just
> TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math
> but "mulv4hf3" with
> TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math &&
> TARGET_MMX_WITH_SSE
I'll add TARGET_MMX_WITH_SSE to divv4hf3 and other v4hf related patterns to
align with other 64-bit vector operation patterns.

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