https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119040
--- Comment #5 from Jeevitha <jeevitha at gcc dot gnu.org> ---
(In reply to Segher Boessenkool from comment #4)
> (In reply to Segher Boessenkool from comment #3)
> > I wonder if our patterns for vsel are correct at all? They seem to do the
> > comparison in some bigger mode, but it should be bitwise?
>
> Not sure what code I was looking at, but our patterns (for vsel and xxsel)
> seem to be correct now. And there is no comparison at all in there, it all
> is bitfiddling as it should be.
The vsel pattern itself looks correct. However, the current combiner is unable
to fold this case because the two const_vector values are treated as distinct
values placed in separate registers. Because of that, combine does not realize
that the (and / and / ior) sequence is equivalent to a vsel.
Below is the RTL dump before combine:
2: r120:V4SI = %2:V4SI
4: r122:V4SI = %4:V4SI
11: r123:V4SI = const_vector(const_int -64)
12: r118:V4SI = r120:V4SI & r123:V4SI
17: r126:V4SI = const_vector(const_int 63)
18: r125:V4SI = r122:V4SI & r126:V4SI
19: r124:V4SI = r125:V4SI | r118:V4SI
To handle this situation, we could introduce a split pattern that checks
whether the two vector values have non-overlapping bits and, if so, rewrites
the operation into a single vsel. I am preparing a patch based on this approach
like below, Is this fine?
(define_insn_and_split "new_merge_pattern"
[(set (match_operand:VM 0 "register_operand" "=wa,v")
(ior:VM
(and:VM (match_operand:VM 1 "register_operand" "wa,v") ;; a
(match_operand:VM 2 "register_operand" "wa,v")) ;; mask1
(and:VM (match_operand:VM 3 "register_operand" "wa,v") ;; b
(match_operand:VM 4 "register_operand" "wa,v"))))] ;; mask2
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)
&& rs6000_vector_masks_overlap_p (operands[2], operands[4])" /* ensure
operand 2 and 4 has non overlapping bits */
"#"
{
/* emit vsel here */
DONE;
})
