https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121959
--- Comment #2 from Li Pan <pan2.li at intel dot com> --- I prepared a draft to verify its accuracy (see attachment). It looks reasonable from the rvv insn dump. However, the initial difference is sign extend or zero extend, see sample below. vsext.vf2 v1,v2 // Compares to vzext.vf2 v8, v10 vsll.vi v1,v1,16 If the v1 is expected to logic shift left high 16 bits of element size 32-bits, the sign extend is totally the same as zero extend. Thus, we can perform this transfer first and then combine the zero extend to vwsll. For example: (set (RVVM1SImode v10) (sign_extend:RVVM1SImode (RVVMF2HImode v11)) (set (RVVM1SImode v12) (lsl:RVVM1SImode (RVVSIMode v10) (const_int 16))) ===> (set (RVVM1SImode v10) (sign_extend:RVVM1SImode (RVVMF2HImode v11)) (set (RVVM1SImode v12) (lsl:RVVM1SImode ((sign_extend:RVVM1SImode (RVVMF2HImode v11) (const_int 16)))
