[Bug target/121548] [15/16 Regression] ICE: SIGSEGV in satisfies_constraint_vu (constraints.md:199) with -O -mrvv-vector-bits=zvl -march=rv64gv

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121548

--- Comment #1 from Jeffrey A. Law <law at gcc dot gnu.org> ---
It looks like we're unconditionally trying to get the merge_op_idx on an insn
that doesn't support that:


(insn 16 15 17 2 (set (subreg:V1DF (reg:RVVM1DF 149 [ _4 ]) 0)
        (mem:V1DF (reg/f:DI 151 [ q ]) [2 *q.1_5+0 S8 A64])) "j.c":9:8 3244
{*movv1df}
     (expr_list:REG_DEAD (reg/f:DI 151 [ q ])
        (nil)))

(define_insn_and_split "*mov<mode>"
  [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
        (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" "  m,vr, vr"))]
  "TARGET_VECTOR
[ ... ]
  [(set_attr "type" "vlde,vste,vmov")
   (set_attr "mode" "<MODE>")
   (set (attr "avl_type_idx") (const_int INVALID_ATTRIBUTE))
   (set (attr "mode_idx") (const_int INVALID_ATTRIBUTE))]


I suspect a suitable attribute setting would be sufficient here.  But I also
suspect there's other insns that will need similar handling.  We should discuss
this in tomorrow's patchwork meeting.