https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119010
--- Comment #12 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Richard Biener <rgue...@gcc.gnu.org>: https://gcc.gnu.org/g:365c82dbf3319e5adb5cced2dae0c4a9aa48f5bc commit r15-8976-g365c82dbf3319e5adb5cced2dae0c4a9aa48f5bc Author: Richard Biener <rguent...@suse.de> Date: Thu Mar 27 08:21:10 2025 +0100 target/119010 - more DFmode handling in zn4zn5 reservations The following adds DFmode where V1DFmode and SFmode were handled. This resolves missing reservations for adds, subs [with memory] and for FMAs for the testcase I'm looking at. Resolved cases are -;; 16--> b 0: i 237 xmm3=xmm3+[r9*0x8+si] :nothing -;; 29--> b 0: i 246 xmm3=xmm3+xmm1 :nothing -;; 46--> b 0: i 296 xmm1=xmm1-xmm3 :nothing I've done search-and-replace for this, the catched cases look reasonable though I'm of course not sure all of them can actually happen. This also fixes the matched type for the znver{4,5}_sse_muladd_load reservations from sseshuf to ssemuladd, resolving -;; 1--> b 0: i 161 xmm0={-xmm0*xmm27+[cx+ax]} :nothing -;; 22--> b 0: i 229 xmm11={-xmm11*xmm7+[di*0x8+dx]} :nothing PR target/119010 * config/i386/zn4zn5.md (znver4_sse_add, znver4_sse_add_load, znver5_sse_add_load, znver4_sse_add1, znver4_sse_add1_load, znver5_sse_add1_load, znver4_sse_mul, znver4_sse_mul_load, znver5_sse_mul_load, znver4_sse_cvt, znver4_sse_cvt_load, znver5_sse_cvt_load, znver4_sse_shuf, znver5_sse_shuf, znver4_sse_shuf_load, znver5_sse_shuf_load, znver4_sse_cmp_avx128, znver5_sse_cmp_avx128, znver4_sse_cmp_avx128_load, znver5_sse_cmp_avx128_load): Also handle DFmode. (znver4_sse_muladd_load, znver5_sse_muladd_load): Use ssemuladd type.
