[Bug target/119010] [15 Regression] 444.namd shows a huge compile-time regression with -mtune=znver5

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119010

--- Comment #13 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Richard Biener <rgue...@gcc.gnu.org>:

https://gcc.gnu.org/g:088ed1042d12f23261bc499b927b93fd61f8d574

commit r15-8977-g088ed1042d12f23261bc499b927b93fd61f8d574
Author: Richard Biener <rguent...@suse.de>
Date:   Thu Mar 27 08:40:32 2025 +0100

    target/119010 - add znver{4,5}_insn_both to resolve missing reservations

    I still was seeing

    ;;        0--> b  0: i 101 {[sp-0x3c]=[sp-0x3c]+0x1;clobber flags;}:nothing

    so the following adds a standard alu insn reservation mimicing that
    from the znver.md description allowing both load and store.

            PR target/119010
            * config/i386/zn4zn5.md (znver4_insn_both, znver5_insn_both):
            New reservation for ALU ops with load and store.