https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118916
Tomas Chang <changyp6 at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|RESOLVED |UNCONFIRMED
Resolution|INVALID |---
--- Comment #5 from Tomas Chang <changyp6 at gmail dot com> ---
(In reply to Andrew Pinski from comment #3)
> str w1, [x2]
> str wzr, [x2], -4
> .L6:
> ldr w1, [x2]
>
> is correct as the gimple code is:
>
> MEM[(volatile unsigned int *)1099193386136B] ={v} 1;
> MEM[(volatile unsigned int *)1099193386136B] ={v} 0;
>
> <bb 3> [local count: 1073741824]:
> _3 ={v} MEM[(volatile unsigned int *)1099193386132B];
>
> That is the load is loading from `the original address - 4`.
>
> If this memory mapped register does NOT support all stores, then you need to
> use inline-asm and NOT volatile.
>
> volatile just talks about the store/loads happening in assembly in the same
> order as written and in the GCC 14.2 case with -O3 they are. But you have
> also a write back or post increment instruction which sets x2 to the next
> address. There is no volatile violation here since the stores/load happen in
> the same. just the memory location does not support all instructions.
Hi Andrew,
Many thanks to your explanation.
I understand this case now.
I also found that the Linux kernel has implemented such code in ASM to make
sure it works in hypervisor mode.
I'll change my code accordingly.
