https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118103
--- Comment #13 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Pan Li <pa...@gcc.gnu.org>: https://gcc.gnu.org/g:55d288d4ff5360c572f2a017ba9385840ac5134e commit r15-7215-g55d288d4ff5360c572f2a017ba9385840ac5134e Author: Pan Li <pan2...@intel.com> Date: Sat Jan 25 15:45:10 2025 +0800 RISC-V: Make FRM as global register [PR118103] After we enabled the labe-combine pass after the mode-switching pass, it will try to combine below insn patterns into op. Aka: (insn 40 5 41 2 (set (reg:SI 11 a1 [151]) (reg:SI 69 frm)) "pr118103-simple.c":67:15 2712 {frrmsi} (nil)) (insn 41 40 7 2 (set (reg:SI 69 frm) (const_int 2 [0x2])) "pr118103-simple.c":69:8 2710 {fsrmsi_restore} (nil)) (insn 42 10 11 2 (set (reg:SI 69 frm) (reg:SI 11 a1 [151])) "pr118103-simple.c":70:8 2710 {fsrmsi_restore} (nil)) trying to combine definition of r11 in: 40: a1:SI=frm:SI into: 42: frm:SI=a1:SI instruction becomes a no-op: (set (reg:SI 69 frm) (reg:SI 69 frm)) original cost = 4 + 4 (weighted: 8.000000), replacement cost = 2147483647; keeping replacement rescanning insn with uid = 42. updating insn 42 in-place verify found no changes in insn with uid = 42. deleting insn 40 For example we have code as blow: 9 â int test_exampe () { 10 â test (); 11 â 12 â size_t vl = 4; 13 â vfloat16m1_t va = __riscv_vle16_v_f16m1(a, vl); 14 â va = __riscv_vfnmadd_vv_f16m1_rm(va, va, va, __RISCV_FRM_RDN, vl); 15 â va = __riscv_vfmsac_vv_f16m1(va, va, va, vl); 16 â 17 â __riscv_vse16_v_f16m1(b, va, vl); 18 â 19 â return 0; 20 â } it will be compiled to: 53 â main: 54 â addi sp,sp,-16 55 â sd ra,8(sp) 56 â call initialize 57 â lui a6,%hi(b) 58 â lui a2,%hi(a) 59 â addi a3,a6,%lo(b) 60 â addi a2,a2,%lo(a) 61 â li a4,4 62 â .L8: 63 â fsrmi 2 64 â vsetvli a5,a4,e16,m1,ta,ma 65 â vle16.v v1,0(a2) 66 â slli a1,a5,1 67 â subw a4,a4,a5 68 â add a2,a2,a1 69 â vfnmadd.vv v1,v1,v1 >> The fsrm a0 insn is deleted by late-combine << 70 â vfmsub.vv v1,v1,v1 71 â vse16.v v1,0(a3) 72 â add a3,a3,a1 73 â bgt a4,zero,.L8 74 â lh a4,%lo(b)(a6) 75 â li a5,-20480 76 â addi a5,a5,-1382 77 â bne a4,a5,.L14 78 â ld ra,8(sp) 79 â li a0,0 80 â addi sp,sp,16 81 â jr ra This patch would like to add the FRM register to the global_regs as it is a cooperatively-managed global register. And then the fsrm insn will not be eliminated by late-combine. The related spec17 cam4 failure may also caused by this issue too. The below test suites are passed for this patch. * The rv64gcv fully regression test. PR target/118103 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_conditional_register_usage): Add the FRM as the global_regs. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr118103-1.c: New test. * gcc.target/riscv/rvv/base/pr118103-run-1.c: New test. Signed-off-by: Pan Li <pan2...@intel.com>
