https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116662
Xi Ruoyao <xry111 at gcc dot gnu.org> changed:
What |Removed |Added
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CC| |xry111 at gcc dot gnu.org
--- Comment #6 from Xi Ruoyao <xry111 at gcc dot gnu.org> ---
> I don't think so. I think it should be set to the largest possible value of
> L1 cache line size. If not, then how does it fulfill the requirement
> "Minimum offset between two objects to avoid false sharing."?
cppreference is not the standard. The standard never says
hardware_destructive_interference_size means this.
Instead it says:
This number is the minimum recommended offset between two concurrently-accessed
objects to avoid additional performance degradation due to contention
introduced by the implementation. It shall be at least alignof(max_align_t).
To me "recommended" means the value is not needed to be strictly matching the
hardware property. And the original paper
https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0154r1.html clearly
says:
Destructive interference size: a number that’s suitable as an offset between
two objects to likely avoid false-sharing due to different runtime access
patterns from different threads.
Note the word "likely" directly contradicts from your suggestion using the
maximum value. If we have 100 CPUs with 32B, 250 CPUs with 64B, and 10 CPUs
with 128B, by "likely" we should use 64B, but the maximum is 128B.
