https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116662
Bug ID: 116662
Summary: Wrong value of __GCC_DESTRUCTIVE_SIZE for riscv64
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: rsworktech at outlook dot com
Target Milestone: ---
Target: riscv64-linux-gnu
As documented on cppreference[1], hardware_destructive_interference_size
provide a portable way to access the L1 data cache line size. And
Raymond mentions hardware_destructive_interference_size tells you
(basically) the size of a cache line in his blog[2].
But this value is 32 for riscv64, which seems wrong to me because IIRC
many riscv64 cpus have cacheline of size 64.
This value is defined to be __GCC_DESTRUCTIVE_SIZE. And Clang takes this
value from gcc when implementing their __GCC_DESTRUCTIVE_SIZE[3]. In
general I am not familiar with the gcc code base and didn't find the
definition of this constant for riscv64 target.
Jonathan told me that 32 is the default value[4] so it is a bug.
[1]:
https://en.cppreference.com/w/cpp/thread/hardware_destructive_interference_size
[2]: https://devblogs.microsoft.com/oldnewthing/20230424-00/?p=108085
[3]: https://github.com/llvm/llvm-project/pull/89446#issuecomment-2070649367
[4]: https://gcc.gnu.org/pipermail/libstdc++/2024-September/059490.html
