https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115188
--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Wilco Dijkstra <wi...@gcc.gnu.org>: https://gcc.gnu.org/g:d04c5537f5ae4a3acd3f5135347d7e2d8c218811 commit r15-1786-gd04c5537f5ae4a3acd3f5135347d7e2d8c218811 Author: Wilco Dijkstra <wilco.dijks...@arm.com> Date: Tue Jul 2 17:37:04 2024 +0100 Arm: Fix disassembly error in Thumb-1 relaxed load/store [PR115188] A Thumb-1 memory operand allows single-register LDMIA/STMIA. This doesn't get printed as LDR/STR with writeback in unified syntax, resulting in strange assembler errors if writeback is selected. To work around this, use the 'Uw' constraint that blocks writeback. Also use a new 'mem_and_no_t1_wback_op' which is a general memory operand that disallows writeback in Thumb-1. A few other patterns were using 'm' for Thumb-1 in a similar way, update these to also use 'mem_and_no_t1_wback_op' and 'Uw'. gcc: PR target/115188 * config/arm/arm.md (unaligned_loadsi): Use 'Uw' constraint and 'mem_and_no_t1_wback_op'. (unaligned_loadhiu): Likewise. (unaligned_storesi): Likewise. (unaligned_storehi): Likewise. * config/arm/predicates.md (mem_and_no_t1_wback_op): Add new predicate. * config/arm/sync.md (arm_atomic_load<mode>): Use 'Uw' constraint. (arm_atomic_store<mode>): Likewise. gcc/testsuite: PR target/115188 * gcc.target/arm/pr115188.c: Add new test.
