https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115634
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Last reconfirmed| |2024-06-25
CC| |pinskia at gcc dot gnu.org
Keywords| |build
Component|rtl-optimization |target
Ever confirmed|0 |1
Status|UNCONFIRMED |NEW
--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
; 64 bit register shift with reg or imm shift count
; sll, srl, sllg, srlg, sllk, srlk
(define_insn "*<shift><mode>3"
[(set (match_operand:GPR 0 "register_operand" "=d, d")
(SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
(match_operand:QI 2 "shift_count_operand" "jsc,jsc")))]
""
"@
s<lr>l<g>\t%0,<1>%Y2
s<lr>l<gk>\t%0,%1,%Y2"
[(set_attr "op_type" "RS<E>,RSY")
(set_attr "atype" "reg,reg")
(set_attr "cpu_facility" "*,z196")
(set_attr "z10prop" "z10_super_E1,*")])
;; Shift count operands are not necessarily legitimate addresses
;; but the predicate shift_count_operand will only allow
;; proper operands. If reload/lra need to change e.g. a spilled register
;; they can still do so via the special handling of address constraints.
;; To avoid further reloading (caused by a non-matching constraint) we
;; always return true here as the predicate's checks are already sufficient.
(define_address_constraint "jsc"
"Address style operand used as shift count."
(match_test "true" ))
(define_predicate "shift_count_operand"
(and (match_code "reg, subreg, and, plus, const_int")
(match_test "CONST_INT_P (op) || GET_MODE (op) == E_QImode"))
{
return s390_valid_shift_count (op, 63);
}
)
s390_valid_shift_count does not seem to check that %r0 was valid here.
This is so ick though.
