https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115634
Bug ID: 115634
Summary: s390 bootstrap failure since r15-1579-g792f97b44ffc5e
Product: gcc
Version: unknown
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: stefansf at gcc dot gnu.org
Target Milestone: ---
Target: s390*-*-*
during RTL pass: final
/devel/src/gcc/rtlanal.cc: In function 'long unsigned int
nonzero_bits1(const_rtx, scalar_int_mode, const_rtx, machine_mode, long
unsigned int)':
/devel/src/gcc/rtlanal.cc:5242:1: internal compiler error: in
print_addrstyle_operand, at config/s390/s390.cc:8143
5242 | }
| ^
0x307b07b print_addrstyle_operand
/devel/src/gcc/config/s390/s390.cc:8143
0x307b1c5 print_shift_count_operand
/devel/src/gcc/config/s390/s390.cc:8170
0x307d0f3 print_operand(_IO_FILE*, rtx_def*, int)
/devel/src/gcc/config/s390/s390.cc:8637
0x2a1f2cf default_print_operand(_IO_FILE*, rtx_def*, int)
/devel/src/gcc/targhooks.cc:366
0x22ede79 output_operand(rtx_def*, int)
/devel/src/gcc/final.cc:3631
0x22ed847 output_asm_insn(char const*, rtx_def**)
/devel/src/gcc/final.cc:3524
0x22ebaf9 final_scan_insn_1
/devel/src/gcc/final.cc:2840
0x22ebd83 final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*)
/devel/src/gcc/final.cc:2886
0x22e9377 final_1
/devel/src/gcc/final.cc:1977
0x22ef45d rest_of_handle_final
/devel/src/gcc/final.cc:4239
0x22ef8c1 execute
/devel/src/gcc/final.cc:4317
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
Prior late-combine we have
(insn 180 1798 182 21 (set (reg:DI 1 %r1 [orig:250 _319 ] [250])
(ashift:DI (reg:DI 1 %r1 [346])
(plus:QI (reg:QI 2 %r2 [orig:61 _2 ] [61])
(const_int -51 [0xffffffffffffffcd])))) 2148 {*ashldi3}
(nil))
and afterwards
(insn 180 179 182 21 (set (reg:DI 1 %r1 [orig:250 _319 ] [250])
(ashift:DI (reg:DI 1 %r1 [346])
(plus:QI (reg:QI 0 %r0 [orig:61 _2 ] [61])
(const_int -51 [0xffffffffffffffcd])))) 2148 {*ashldi3}
(nil))
The culprit is that hreg %r0 is not allowed for shift amounts where if the
address operand has a base register, then it must be a register 1 to 15. I
guess this is coming from
trying to combine definition of r2 in:
1798: %r2:QI=%r0:QI
into:
180: %r1:DI=%r1:DI<<%r2:QI-0x33
successfully matched this instruction to *ashldi3:
(set (reg:DI 1 %r1 [orig:250 _319 ] [250])
(ashift:DI (reg:DI 1 %r1 [346])
(plus:QI (reg:QI 0 %r0 [orig:61 _2 ] [61])
(const_int -51 [0xffffffffffffffcd]))))
original cost = 4 + 8 (weighted: 0.241703), replacement cost = 8 (weighted:
0.161135); keeping replacement
rescanning insn with uid = 180.
updating insn 180 in-place
verify found no changes in insn with uid = 180.
