https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113779
--- Comment #5 from Miro Kropacek <miro.kropacek at gmail dot com> --- I have been told that one of the reasons why post-incrementing modes are not supported / preferred these days is that they halt the CPU pipeline (of course, totally not applicable on m68k). So with the offsets you can parallelize the movements while when post-incrementing the values of a1, you always have to wait for the previous instruction to finish. So I could understand that this has been changed but it definitely shouldn't be a change involving all possible CPUs.
