https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112648
JuzheZhong <juzhe.zhong at rivai dot ai> changed:
What |Removed |Added
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CC| |juzhe.zhong at rivai dot ai
--- Comment #4 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Rather than talk about the compile option.
I confirm the riscv-autovec-lmul is correct.
https://godbolt.org/z/nzfWE98n7
It does using e32m1 for vectorized codes:
vsetvli zero,a3,e32,m1,ta,ma
vfcvt.f.x.v v2,v1
vfcvt.rtz.x.f.v v2,v2
vse32.v v2,0(a5)
It definitely correct.
The reason you saw:
vsetvli a3,a4,e8,mf4,ta,ma
Plz note that this is not the vsetvl to configure the vectorized codes
operations.
It just a instruction calculating the elements to be processed for each
iterator.
It's generated by SELECT_VL pattern.
So, for SELECT_VL here,
vsetvli a3,a4,e8,mf4,ta,ma or vsetvli a3,a4,e32,m1,ta,ma are correct.
Since they are having same ratio.
More details on risc-v v spec.
